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Message-ID: <41d02cf11098269af44d06ba7c9930ae4a5e83a2.camel@mediatek.com>
Date: Mon, 4 Nov 2024 02:35:13 +0000
From: CK Hu (胡俊光) <ck.hu@...iatek.com>
To: "sumit.semwal@...aro.org" <sumit.semwal@...aro.org>,
"christian.koenig@....com" <christian.koenig@....com>, "mchehab@...nel.org"
<mchehab@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
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<matthias.bgg@...il.com>, "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Shu-hsiang Yang (楊舒翔)
<Shu-hsiang.Yang@...iatek.com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
"yunkec@...omium.org" <yunkec@...omium.org>, "linaro-mm-sig@...ts.linaro.org"
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<devicetree@...r.kernel.org>, Yaya Chang (張雅清)
<Yaya.Chang@...iatek.com>, Project_Global_Chrome_Upstream_Group
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<hidenorik@...omium.org>, Shun-Yi Wang (王順億)
<Shun-Yi.Wang@...iatek.com>
Subject: Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw
unit
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@...iatek.com>
> ---
[snip]
> +void mtk_cam_dump_req_rdy_status(struct device *dev,
> + void __iomem *base, void __iomem *yuvbase)
> +{
This function is useless, so drop it.
Regards,
CK
> + dev_dbg_ratelimited(dev,
> + "REQ RAW/2/3 DMA/2:%08x/%08x/%08x/%08x/%08x\n",
> + readl_relaxed(base + REG_CTL_RAW_MOD_REQ_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD2_REQ_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD3_REQ_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD5_REQ_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD6_REQ_STAT));
> + dev_dbg_ratelimited(dev,
> + "RDY RAW/2/3 DMA/2:%08x/%08x/%08x/%08x/%08x\n",
> + readl_relaxed(base + REG_CTL_RAW_MOD_RDY_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD2_RDY_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD3_RDY_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD5_RDY_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD6_RDY_STAT));
> + dev_dbg_ratelimited(dev,
> + "REQ YUV/2/3/4 WDMA:%08x/%08x/%08x/%08x/%08x\n",
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD_REQ_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD2_REQ_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD3_REQ_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD4_REQ_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD5_REQ_STAT));
> + dev_dbg_ratelimited(dev,
> + "RDY YUV/2/3/4 WDMA:%08x/%08x/%08x/%08x/%08x\n",
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD_RDY_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD2_RDY_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD3_RDY_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD4_RDY_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD5_RDY_STAT));
> +}
> +
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