[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <Zyns0qfYpO3mZ4fa@linaro.org>
Date: Tue, 5 Nov 2024 12:00:50 +0200
From: Abel Vesa <abel.vesa@...aro.org>
To: "Peng Fan (OSS)" <peng.fan@....nxp.com>
Cc: Abel Vesa <abelvesa@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
Aisheng Dong <aisheng.dong@....com>, linux-clk@...r.kernel.org,
imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, Peng Fan <peng.fan@....com>,
Jacky Bai <ping.bai@....com>
Subject: Re: [PATCH v3 3/5] clk: imx: fracn-gppll: fix pll power up
On 24-10-27 20:00:09, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@....com>
>
> To i.MX93 which features dual Cortex-A55 cores and DSU, when using
> writel_relaxed to write value to PLL registers, the value might be
> buffered. To make sure the value has been written into the hardware,
> using readl to read back the register could achieve the goal.
>
> current PLL power up flow can be simplified as below:
> 1. writel_relaxed to set the PLL POWERUP bit;
> 2. readl_poll_timeout to check the PLL lock bit:
> a). timeout = ktime_add_us(ktime_get(), timeout_us);
> b). readl the pll the lock reg;
> c). check if the pll lock bit ready
> d). check if timeout
>
> But in some corner cases, both the write in step 1 and read in
> step 2 will be blocked by other bus transaction in the SoC for a
> long time, saying the value into real hardware is just before step b).
> That means the timeout counting has begins for quite sometime since
> step a), but value still not written into real hardware until bus
> released just at a point before step b).
>
> Then there maybe chances that the pll lock bit is not ready
> when readl done but the timeout happens. readl_poll_timeout will
> err return due to timeout. To avoid such unexpected failure,
> read back the reg to make sure the write has been done in HW
> reg.
>
> So use readl after writel_relaxed to fix the issue.
>
> Since we are here, to avoid udelay to run before writel_relaxed, use
> readl before udelay.
>
> Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
> Co-developed-by: Jacky Bai <ping.bai@....com>
> Signed-off-by: Jacky Bai <ping.bai@....com>
> Signed-off-by: Peng Fan <peng.fan@....com>
Reviewed-by: Abel Vesa <abel.vesa@...aro.org>
> ---
> drivers/clk/imx/clk-fracn-gppll.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
> index 4749c3e0b7051cf53876664808aa28742f6861f7..85771afd4698ae6a0d8a7e82193301e187049255 100644
> --- a/drivers/clk/imx/clk-fracn-gppll.c
> +++ b/drivers/clk/imx/clk-fracn-gppll.c
> @@ -254,9 +254,11 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate,
> pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv |
> FIELD_PREP(PLL_MFI_MASK, rate->mfi);
> writel_relaxed(pll_div, pll->base + PLL_DIV);
> + readl(pll->base + PLL_DIV);
> if (pll->flags & CLK_FRACN_GPPLL_FRACN) {
> writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
> writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
> + readl(pll->base + PLL_NUMERATOR);
> }
>
> /* Wait for 5us according to fracn mode pll doc */
> @@ -265,6 +267,7 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate,
> /* Enable Powerup */
> tmp |= POWERUP_MASK;
> writel_relaxed(tmp, pll->base + PLL_CTRL);
> + readl(pll->base + PLL_CTRL);
>
> /* Wait Lock */
> ret = clk_fracn_gppll_wait_lock(pll);
> @@ -302,6 +305,7 @@ static int clk_fracn_gppll_prepare(struct clk_hw *hw)
>
> val |= POWERUP_MASK;
> writel_relaxed(val, pll->base + PLL_CTRL);
> + readl(pll->base + PLL_CTRL);
>
> ret = clk_fracn_gppll_wait_lock(pll);
> if (ret)
>
> --
> 2.37.1
>
Powered by blists - more mailing lists