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Message-Id: <20241106-mbly-clk-v2-2-84cfefb3f485@bootlin.com>
Date: Wed, 06 Nov 2024 17:03:53 +0100
From: Théo Lebrun <theo.lebrun@...tlin.com>
To: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>,
Grégory Clement <gregory.clement@...tlin.com>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Cc: linux-mips@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Tawfik Bayouk <tawfik.bayouk@...ileye.com>,
Théo Lebrun <theo.lebrun@...tlin.com>
Subject: [PATCH v2 02/10] dt-bindings: clock: eyeq: add more Mobileye
EyeQ5/EyeQ6H clocks
Add #defines for Mobileye clock controller:
- EyeQ5 core 0 thru 3 clocks. Internally:
EQ5C_PLL_CPU: already exposed
└── EQ5C_CPU_OCC: unexposed, no reason to do so
├── EQ5C_CPU_CORE0: new!
├── EQ5C_CPU_CORE1: new!
├── EQ5C_CPU_CORE2: new!
└── EQ5C_CPU_CORE3: new!
- EyeQ5 peripheral clocks. Internally:
EQ5C_PLL_PER: already exposed
├── EQ5C_PER_OCC: new!
│ ├── EQ5C_PER_SPI: new!
│ ├── EQ5C_PER_I2C: new!
│ ├── EQ5C_PER_GPIO: new!
│ └── EQ5C_PER_UART: new!
├── EQ5C_PER_EMMC: new!
└── EQ5C_PER_OCC_PCI: new!
- EyeQ6H central OLB. Internally:
EQ6HC_CENTRAL_PLL_CPU: new!
└── EQ6HC_CENTRAL_CPU_OCC: new!
- EyeQ6H west OLB. Internally:
EQ6HC_WEST_PLL_PER: new!
└── EQ6HC_WEST_PER_OCC: new!
└── EQ6HC_WEST_PER_UART: new!
Signed-off-by: Théo Lebrun <theo.lebrun@...tlin.com>
---
include/dt-bindings/clock/mobileye,eyeq5-clk.h | 44 +++++++++++++++++++-------
1 file changed, 33 insertions(+), 11 deletions(-)
diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
index b433c1772c28fae818b3a6ba428d1f89000f9206..f353c2988035f7c9fb84e4b59c6c4a220436454b 100644
--- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
+++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
@@ -6,24 +6,46 @@
#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
-#define EQ5C_PLL_CPU 0
-#define EQ5C_PLL_VMP 1
-#define EQ5C_PLL_PMA 2
-#define EQ5C_PLL_VDI 3
-#define EQ5C_PLL_DDR0 4
-#define EQ5C_PLL_PCI 5
-#define EQ5C_PLL_PER 6
-#define EQ5C_PLL_PMAC 7
-#define EQ5C_PLL_MPC 8
-#define EQ5C_PLL_DDR1 9
+#define EQ5C_PLL_CPU 0
+#define EQ5C_PLL_VMP 1
+#define EQ5C_PLL_PMA 2
+#define EQ5C_PLL_VDI 3
+#define EQ5C_PLL_DDR0 4
+#define EQ5C_PLL_PCI 5
+#define EQ5C_PLL_PER 6
+#define EQ5C_PLL_PMAC 7
+#define EQ5C_PLL_MPC 8
+#define EQ5C_PLL_DDR1 9
-#define EQ5C_DIV_OSPI 10
+#define EQ5C_DIV_OSPI 10
+
+/* EQ5C_PLL_CPU children */
+#define EQ5C_CPU_CORE0 11
+#define EQ5C_CPU_CORE1 12
+#define EQ5C_CPU_CORE2 13
+#define EQ5C_CPU_CORE3 14
+
+/* EQ5C_PLL_PER children */
+#define EQ5C_PER_OCC 15
+#define EQ5C_PER_UART 16
+#define EQ5C_PER_SPI 17
+#define EQ5C_PER_I2C 18
+#define EQ5C_PER_GPIO 19
+#define EQ5C_PER_EMMC 20
+#define EQ5C_PER_OCC_PCI 21
#define EQ6LC_PLL_DDR 0
#define EQ6LC_PLL_CPU 1
#define EQ6LC_PLL_PER 2
#define EQ6LC_PLL_VDI 3
+#define EQ6HC_CENTRAL_PLL_CPU 0
+#define EQ6HC_CENTRAL_CPU_OCC 1
+
+#define EQ6HC_WEST_PLL_PER 0
+#define EQ6HC_WEST_PER_OCC 1
+#define EQ6HC_WEST_PER_UART 2
+
#define EQ6HC_SOUTH_PLL_VDI 0
#define EQ6HC_SOUTH_PLL_PCIE 1
#define EQ6HC_SOUTH_PLL_PER 2
--
2.47.0
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