linux-kernel - [PATCH v2 0/2] Enable emmc and SD on QCS615

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Message-Id: <20241106072343.2070933-1-quic_yuanjiey@quicinc.com>
Date: Wed,  6 Nov 2024 15:23:41 +0800
From: Yuanjie Yang <quic_yuanjiey@...cinc.com>
To: ulf.hansson@...aro.org, robh@...nel.org, krzk+dt@...nel.org,
        conor+dt@...nel.org, bhupesh.sharma@...aro.org, andersson@...nel.org,
        konradybcio@...nel.org
Cc: linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        quic_tingweiz@...cinc.com, quic_yuanjiey@...cinc.com
Subject: [PATCH v2 0/2] Enable emmc and SD on QCS615

Add SDHC1 and SDHC2 support to the QCS615 Ride platform. The SDHC1
and SDHC2 of QCS615 are derived from SM6115. Include the relevant
binding documents accordingly. Additionally, configure SDHC1-related
and SDHC2-related opp, power, and interconnect settings in the device
tree.

Signed-off-by: Yuanjie Yang <quic_yuanjiey@...cinc.com>
---
This patch series depends on below patch series:
https://lore.kernel.org/all/20241104-add_initial_support_for_qcs615-v5-0-9dde8d7b80b0@quicinc.com/
https://lore.kernel.org/all/20241105032107.9552-1-quic_qqzhou@quicinc.com/

Changes in v2:
- Improve the commit messages and cover letter
- Remove applied patches 1
- Pad sdhc_1 node and sdhc_2 node register addresses to 8 hex digits
- Adjust sdhc_1 node and sdhc_2 node register addresses to hexadecimal
- Modify sdhc_2 vqmmc-supply incorrect power configuration
- Link to v1: https://lore.kernel.org/all/20241023092708.604195-1-quic_yuanjiey@quicinc.com/

---
Yuanjie Yang (2):
  arm64: dts: qcom: qcs615: add SDHC1 and SDHC2
  arm64: dts: qcom: qcs615-ride: Enable SDHC1 and SDHC2

 arch/arm64/boot/dts/qcom/qcs615-ride.dts |  31 ++++
 arch/arm64/boot/dts/qcom/qcs615.dtsi     | 198 +++++++++++++++++++++++
 2 files changed, 229 insertions(+)

-- 
2.34.1