[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <Zys4qs-uHvISaaPB@ryzen>
Date: Wed, 6 Nov 2024 10:36:42 +0100
From: Niklas Cassel <cassel@...nel.org>
To: Frank Li <Frank.Li@....com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>, Arnd Bergmann <arnd@...db.de>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
imx@...ts.linux.dev, dlemoal@...nel.org, maz@...nel.org,
tglx@...utronix.de, jdmason@...zu.us
Subject: Re: [PATCH v4 0/5] PCI: EP: Add RC-to-EP doorbell with platform MSI
controller
On Wed, Nov 06, 2024 at 10:15:27AM +0100, Niklas Cassel wrote:
>
> I do get a domain, but I do not get any IRQ on the EP side when the RC side is
> writing the doorbell (as part of pcitest -B),
>
> [ 7.978984] pci_epc_alloc_doorbell: num_db: 1
> [ 7.979545] pci_epf_test_bind: doorbell_addr: 0x40
> [ 7.979978] pci_epf_test_bind: doorbell_data: 0x0
> [ 7.980397] pci_epf_test_bind: doorbell_bar: 0x1
> [ 21.114613] pci_epf_enable_doorbell db_bar: 1
> [ 21.115001] pci_epf_enable_doorbell: doorbell_addr: 0xfe650040
> [ 21.115512] pci_epf_enable_doorbell: phys_addr: 0xfe650000
> [ 21.115994] pci_epf_enable_doorbell: success
>
> # cat /proc/interrupts | grep epc
> 117: 0 0 0 0 0 0 0 0 ITS-pMSI-a40000000.pcie-ep 0 Edge pci-epc-doorbell0
>
> Even if I try to write the doorbell manually from EP side using devmem:
>
> # devmem 0xfe670040 32 1
Sorry, this should of course have been:
# devmem 0xfe650040 32 1
But the result is the name, no IRQ triggered on the EP side.
(My command above was from testing "msi-parent = <&its0 0x0000>",
rather than &its1, but that also didn't work when writing the
corresponding "doorbell_addr" using e.g. devmem.)
Considering that the RC node is using &its1, that is probably
also what should be used in the EP node when running the controller
in EP mode instead of RC mode.
Kind regards,
Niklas
Powered by blists - more mailing lists