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Message-ID: <20241106123758.423584-3-heiko@sntech.de>
Date: Wed, 6 Nov 2024 13:37:57 +0100
From: Heiko Stuebner <heiko@...ech.de>
To: heiko@...ech.de
Cc: quentin.schulz@...rry.de,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Heiko Stuebner <heiko.stuebner@...rry.de>
Subject: [PATCH 2/3] arm64: dts: rockchip: add dsi controller nodes on rk3588
From: Heiko Stuebner <heiko.stuebner@...rry.de>
The RK3588 comes with two DSI2 controllers based on a new Synopsis IP.
Add the necessary nodes for them.
Signed-off-by: Heiko Stuebner <heiko.stuebner@...rry.de>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 56 +++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 8c95c56e8097..6d31de2a6930 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1414,6 +1414,62 @@ i2s9_8ch: i2s@...fc000 {
status = "disabled";
};
+ dsi0: dsi@...20000 {
+ compatible = "rockchip,rk3588-mipi-dsi2";
+ reg = <0x0 0xfde20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
+ clock-names = "pclk", "sys";
+ resets = <&cru SRST_P_DSIHOST0>;
+ reset-names = "apb";
+ power-domains = <&power RK3588_PD_VOP>;
+ phys = <&mipidcphy0>;
+ phy-names = "dcphy";
+ rockchip,grf = <&vop_grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi0_in: port@0 {
+ reg = <0>;
+ };
+
+ dsi0_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ dsi1: dsi@...30000 {
+ compatible = "rockchip,rk3588-mipi-dsi2";
+ reg = <0x0 0xfde30000 0x0 0x10000>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>;
+ clock-names = "pclk", "sys";
+ resets = <&cru SRST_P_DSIHOST1>;
+ reset-names = "apb";
+ power-domains = <&power RK3588_PD_VOP>;
+ phys = <&mipidcphy1>;
+ phy-names = "dcphy";
+ rockchip,grf = <&vop_grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi1_in: port@0 {
+ reg = <0>;
+ };
+
+ dsi1_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
hdmi0: hdmi@...80000 {
compatible = "rockchip,rk3588-dw-hdmi-qp";
reg = <0x0 0xfde80000 0x0 0x20000>;
--
2.45.2
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