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Message-ID: <d410c617-7917-4776-967b-058817f40022@linux.alibaba.com>
Date: Thu, 7 Nov 2024 09:42:32 +0800
From: Baolin Wang <baolin.wang@...ux.alibaba.com>
To: Stanislav Jakubek <stano.jakubek@...il.com>, Rob Herring
 <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Orson Zhai <orsonzhai@...il.com>,
 Chunyan Zhang <zhang.lyra@...il.com>
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 5/5] arm64: dts: sprd: sc9863a: reorder clocks,
 clock-names per bindings



On 2024/11/7 03:05, Stanislav Jakubek wrote:
> DT bindings expect the SC9863A clock-controller clocks/clock-names to be
> in a specific order, reorder them.
> 
> Signed-off-by: Stanislav Jakubek <stano.jakubek@...il.com>

Thanks.
Reviewed-by: Baolin Wang <baolin.wang@...ux.alibaba.com>

> ---
> Changes in V2:
> - new patch
> 
>   arch/arm64/boot/dts/sprd/sc9863a.dtsi | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi
> index 31172ac44adc..e97000e560e7 100644
> --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi
> +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi
> @@ -163,18 +163,18 @@ gic: interrupt-controller@...00000 {
>   		ap_clk: clock-controller@...00000 {
>   			compatible = "sprd,sc9863a-ap-clk";
>   			reg = <0 0x21500000 0 0x1000>;
> -			clocks = <&ext_32k>, <&ext_26m>;
> -			clock-names = "ext-32k", "ext-26m";
> +			clocks = <&ext_26m>, <&ext_32k>;
> +			clock-names = "ext-26m", "ext-32k";
>   			#clock-cells = <1>;
>   		};
>   
>   		aon_clk: clock-controller@...d0000 {
>   			compatible = "sprd,sc9863a-aon-clk";
>   			reg = <0 0x402d0000 0 0x1000>;
> -			clocks = <&ext_26m>, <&rco_100m>,
> -				 <&ext_32k>, <&ext_4m>;
> -			clock-names = "ext-26m", "rco-100m",
> -				      "ext-32k", "ext-4m";
> +			clocks = <&ext_26m>, <&ext_32k>,
> +				 <&ext_4m>, <&rco_100m>;
> +			clock-names = "ext-26m", "ext-32k",
> +				      "ext-4m", "rco-100m";
>   			#clock-cells = <1>;
>   		};
>   

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