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Message-ID: <mafs0cyj77zdm.fsf@kernel.org>
Date: Thu, 07 Nov 2024 17:00:21 +0000
From: Pratyush Yadav <pratyush@...nel.org>
To: Cheng Ming Lin <linchengming884@...il.com>
Cc: tudor.ambarus@...aro.org, pratyush@...nel.org, mwalle@...nel.org,
miquel.raynal@...tlin.com, richard@....at, vigneshr@...com,
linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org,
alvinzhou@...c.com.tw, leoyu@...c.com.tw, Cheng Ming Lin
<chengminglin@...c.com.tw>
Subject: Re: [PATCH] mtd: spi-nor: core: replace dummy buswidth from addr to
data
On Thu, Nov 07 2024, Cheng Ming Lin wrote:
> From: Cheng Ming Lin <chengminglin@...c.com.tw>
>
> The default dummy cycle for Macronix SPI NOR flash in Octal Output
> Read Mode(1-1-8) is 20.
>
> Currently, the dummy buswidth is set according to the address bus width.
> In the 1-1-8 mode, this means the dummy buswidth is 1. When converting
> dummy cycles to bytes, this results in 20 x 1 / 8 = 2 bytes, causing the
> host to read data 4 cycles too early.
>
> Since the protocol data buswidth is always greater than or equal to the
> address buswidth. Setting the dummy buswidth to match the data buswidth
> increases the likelihood that the dummy cycle-to-byte conversion will be
> divisible, preventing the host from reading data prematurely.
Makes sense.
Reviewed-by: Pratyush Yadav <pratyush@...nel.org>
--
Regards,
Pratyush Yadav
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