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Message-ID: <Zy00AoxE0_8p5xCY@intel.com>
Date: Thu, 7 Nov 2024 16:41:22 -0500
From: Rodrigo Vivi <rodrigo.vivi@...el.com>
To: Alexander Usyskin <alexander.usyskin@...el.com>
CC: Miquel Raynal <miquel.raynal@...tlin.com>, Richard Weinberger
<richard@....at>, Vignesh Raghavendra <vigneshr@...com>, Lucas De Marchi
<lucas.demarchi@...el.com>, Thomas Hellström
<thomas.hellstrom@...ux.intel.com>, Maarten Lankhorst
<maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>, Jani Nikula <jani.nikula@...ux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@...ux.intel.com>, Tvrtko Ursulin
<tursulin@...ulin.net>, Oren Weil <oren.jer.weil@...el.com>,
<linux-mtd@...ts.infradead.org>, <dri-devel@...ts.freedesktop.org>,
<intel-gfx@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 08/10] drm/i915/nvm: add support for access mode
On Thu, Nov 07, 2024 at 03:13:54PM +0200, Alexander Usyskin wrote:
> Check NVM access mode from GSC FW status registers
> and overwrite access status read from SPI descriptor, if needed.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@...el.com>
>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@...el.com>
> ---
> drivers/gpu/drm/i915/intel_nvm.c | 25 ++++++++++++++++++++++++-
> 1 file changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_nvm.c b/drivers/gpu/drm/i915/intel_nvm.c
> index 214c4d47a9cd..cbd776e667ad 100644
> --- a/drivers/gpu/drm/i915/intel_nvm.c
> +++ b/drivers/gpu/drm/i915/intel_nvm.c
> @@ -10,6 +10,7 @@
> #include "intel_nvm.h"
>
> #define GEN12_GUNIT_NVM_SIZE 0x80
> +#define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3)
>
> static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] = {
> [0] = { .name = "DESCRIPTOR", },
> @@ -22,6 +23,28 @@ static void i915_nvm_release_dev(struct device *dev)
> {
> }
>
> +static bool i915_nvm_writeable_override(struct drm_i915_private *i915)
> +{
> + resource_size_t base;
> + bool writeable_override;
> +
> + if (IS_DG1(i915)) {
> + base = DG1_GSC_HECI2_BASE;
> + } else if (IS_DG2(i915)) {
> + base = DG2_GSC_HECI2_BASE;
> + } else {
> + drm_err(&i915->drm, "Unknown platform\n");
> + return true;
> + }
> +
> + writeable_override =
> + !(intel_uncore_read(&i915->uncore, HECI_FWSTS(base, 2)) &
> + HECI_FW_STATUS_2_NVM_ACCESS_MODE);
> + if (writeable_override)
> + drm_info(&i915->drm, "NVM access overridden by jumper\n");
> + return writeable_override;
> +}
> +
> void intel_nvm_init(struct drm_i915_private *i915)
> {
> struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> @@ -43,7 +66,7 @@ void intel_nvm_init(struct drm_i915_private *i915)
>
> nvm = i915->nvm;
>
> - nvm->writeable_override = true;
> + nvm->writeable_override = i915_nvm_writeable_override(i915);
> nvm->bar.parent = &pdev->resource[0];
> nvm->bar.start = GEN12_GUNIT_NVM_BASE + pdev->resource[0].start;
> nvm->bar.end = nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1;
> --
> 2.43.0
>
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