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Message-ID: <20241107041509.824457-5-sowon.na@samsung.com>
Date: Thu, 7 Nov 2024 13:15:05 +0900
From: Sowon Na <sowon.na@...sung.com>
To: robh@...nel.org, krzk@...nel.org, conor+dt@...nel.org, vkoul@...nel.org,
alim.akhtar@...sung.com, kishon@...nel.org
Cc: krzk+dt@...nel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
sowon.na@...sung.com
Subject: [PATCH 3/3] arm64: dts: exynosautov920: add ufs phy for
exynosautov920 SoC
Add UFS Phy for exynosautov920
Like exynosautov9, this also uses fixed-rate clock nodes until clock driver
has been supported. The clock nodes are initialized on bootloader stage
thus we don't need to control them so far.
Signed-off-by: Sowon Na <sowon.na@...sung.com>
---
arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index c759134c909e..505ba04722de 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -361,6 +361,17 @@ pinctrl_aud: pinctrl@...60000 {
compatible = "samsung,exynosautov920-pinctrl";
reg = <0x1a460000 0x10000>;
};
+
+ ufs_0_phy: phy@...04000 {
+ compatible = "samsung,exynosautov920-ufs-phy";
+ reg = <0x16e04000 0x4000>;
+ reg-names = "phy-pma";
+ clocks = <&xtcxo>;
+ clock-names = "ref_clk";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
};
timer {
--
2.45.2
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