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Message-ID: <f9f66565-6356-4b61-8653-1e9c006b892c@kernel.org>
Date: Thu, 7 Nov 2024 10:55:16 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Krishna Kurapati <quic_kriskura@...cinc.com>,
 Uttkarsh Aggarwal <quic_uaggarwa@...cinc.com>
Cc: Krzysztof Kozlowski <krzk+dt@...nel.org>, Rob Herring <robh@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>,
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
 Felipe Balbi <balbi@...nel.org>, Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
 linux-usb@...r.kernel.org, linux-kernel@...r.kernel.org,
 devicetree@...r.kernel.org, quic_ppratap@...cinc.com, quic_jackp@...cinc.com
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: snps,dwc3: Add
 snps,filter-se0-fsls-eop quirk

On 07/11/2024 07:17, Krishna Kurapati wrote:
> 
> 
> On 10/18/2024 11:57 AM, Krzysztof Kozlowski wrote:
>> On Thu, Oct 17, 2024 at 05:10:54PM +0530, Uttkarsh Aggarwal wrote:
>>> Adding a new 'snps,filter-se0-fsls-eop quirk' DT quirk to dwc3 core to set
>>> GUCTL1 BIT 29. When set, controller will ignore single SE0 glitch on the
>>> linestate during transmission. Only two or more SE0 is considered as
>>> valid EOP on FS/LS port. This bit is applicable only in FS in device mode
>>> and FS/LS mode of operation in host mode.
>>
>> Why this is not device/compatible specific? Just like all other quirks
>> pushed last one year.
> 
> Hi Krzysztof,
> 
>   Apologies for a late reply from our end.
> 
>   In DWC3 core/dwc3-qcom atleast, there have been no compatible specific 
> quirks added. 

Nothing stops from adding these, I think.

> Also since this is a property of the Synopsys controller
> hardware and not QC specific one, can we add it in bindings itself. 
> Because this is a property other vendors might also use and adding it 
> via compatible might not be appropriate.

This does no answer my question. I don't see how this is not related to
one specific piece of SoC.

If you claim this is board-related, not SoC, give some arguments.
Repeating the same is just no helping.

Best regards,
Krzysztof


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