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Message-ID: <4m26zy7gfxlwfaid5v7yds5sitwqlojqd3h4hpnar73fi6ll6f@iy3moda672ls>
Date: Thu, 7 Nov 2024 11:49:48 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Claudiu <claudiu.beznea@...on.dev>
Cc: geert+renesas@...der.be, mturquette@...libre.com, sboyd@...nel.org, 
	robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, 
	biju.das.jz@...renesas.com, prabhakar.mahadev-lad.rj@...renesas.com, lgirdwood@...il.com, 
	broonie@...nel.org, magnus.damm@...il.com, linus.walleij@...aro.org, 
	support.opensource@...semi.com, perex@...ex.cz, tiwai@...e.com, p.zabel@...gutronix.de, 
	Adam.Thomson.Opensource@...semi.com, linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-sound@...r.kernel.org, 
	linux-gpio@...r.kernel.org, Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH 03/31] dt-bindings: clock: versaclock3: Document 5L35023
 Versa3 clock generator

On Wed, Nov 06, 2024 at 10:17:58AM +0200, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> 
> There are some differences b/w 5L35023 and 5P35023 Versa3 clock
> generator variants but the same driver could be used with minimal
> adjustments. The identified differences are PLL2 Fvco, the clock sel
> bit for SE2 clock and different default values for some registers.

This is one of the best commit messages I saw for such simple binding
change. Much appreciated, thank you.

> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> ---
>  Documentation/devicetree/bindings/clock/renesas,5p35023.yaml | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>

Best regards,
Krzysztof


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