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Message-ID: <90f8aaf2-ef9c-4777-b8db-17fc7c6cf41b@intel.com>
Date: Fri, 8 Nov 2024 12:10:47 -0800
From: Dave Hansen <dave.hansen@...el.com>
To: Rik van Riel <riel@...riel.com>, Dave Hansen <dave.hansen@...ux.intel.com>
Cc: Andy Lutomirski <luto@...nel.org>, Peter Zijlstra <peterz@...radead.org>,
 Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>,
 Borislav Petkov <bp@...en8.de>, x86@...nel.org,
 "H. Peter Anvin" <hpa@...or.com>, linux-kernel@...r.kernel.org,
 kernel-team@...a.com
Subject: Re: [PATCH] x86,tlb: update mm_cpumask lazily

On 11/8/24 12:07, Rik van Riel wrote:
> On Fri, 2024-11-08 at 12:03 -0800, Dave Hansen wrote:
>> On 11/8/24 11:31, Rik van Riel wrote:
>>>  		/* Start receiving IPIs and then read tlb_gen (and
>>> LAM below) */
>>> -		if (next != &init_mm)
>>> +		if (next != &init_mm && !cpumask_test_cpu(cpu,
>>> mm_cpumask(next)))
>>>  			cpumask_set_cpu(cpu, mm_cpumask(next));
>>>  		next_tlb_gen = atomic64_read(&next-
>>>> context.tlb_gen);
>> If we're worried about contention on mm_cpumask(), then this hunk
>> makes
>> sense independently of the lazy updating. We might want to take this
>> hunk forward before we do the rest because this seems like a no-
>> brainer.
>>
> If we always clear the CPU in the mm_cpumask when prev != next,
> wouldn't that result in that CPU's bit being clear (and needing
> to be set) for next when prev != next?
> 
> What am I missing?

Oh, good point.  This is all in the (prev != next) block so yeah, the
bit _has_ to be clear.  Silly me.

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