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Message-Id: <20241108033437.2727574-1-lixianglai@loongson.cn>
Date: Fri, 8 Nov 2024 11:34:37 +0800
From: Xianglai Li <lixianglai@...ngson.cn>
To: linux-kernel@...r.kernel.org
Cc: Bibo Mao <maobibo@...ngson.cn>,
Huacai Chen <chenhuacai@...nel.org>,
kvm@...r.kernel.org,
loongarch@...ts.linux.dev,
Paolo Bonzini <pbonzini@...hat.com>,
Tianrui Zhao <zhaotianrui@...ngson.cn>,
WANG Xuerui <kernel@...0n.name>,
Xianglai li <lixianglai@...ngson.cn>
Subject: [PATCH V4 00/11] Added Interrupt controller emulation for loongarch kvm
Before this, the interrupt controller simulation has been completed
in the user mode program. In order to reduce the loss caused by frequent
switching of the virtual machine monitor from kernel mode to user mode
when the guest accesses the interrupt controller, we add the interrupt
controller simulation in kvm.
The following is a virtual machine simulation diagram of interrupted
connections:
+-----+ +---------+ +-------+
| IPI |--> | CPUINTC | <-- | Timer |
+-----+ +---------+ +-------+
^
|
+---------+
| EIOINTC |
+---------+
^ ^
| |
+---------+ +---------+
| PCH-PIC | | PCH-MSI |
+---------+ +---------+
^ ^ ^
| | |
+--------+ +---------+ +---------+
| UARTs | | Devices | | Devices |
+--------+ +---------+ +---------+
In this series of patches, we mainly realized the simulation of
IPI EIOINTC PCH-PIC interrupt controller.
The simulation of IPI EIOINTC PCH-PIC interrupt controller mainly
completes the creation simulation of the interrupt controller,
the register address space read and write simulation,
and the interface with user mode to obtain and set the interrupt
controller state for the preservation,
recovery and migration of virtual machines.
IPI simulation implementation reference:
https://github.com/loongson/LoongArch-Documentation/tree/main/docs/Loongson-3A5000-usermanual-EN/inter-processor-interrupts-and-communication
EIOINTC simulation implementation reference:
https://github.com/loongson/LoongArch-Documentation/tree/main/docs/Loongson-3A5000-usermanual-EN/io-interrupts/extended-io-interrupts
PCH-PIC simulation implementation reference:
https://github.com/loongson/LoongArch-Documentation/blob/main/docs/Loongson-7A1000-usermanual-EN/interrupt-controller.adoc
For PCH-MSI, we used irqfd mechanism to send the interrupt signal
generated by user state to kernel state and then to EIOINTC without
maintaining PCH-MSI state in kernel state.
You can easily get the code from the link below:
the kernel:
https://github.com/lixianglai/linux
the branch is: interrupt-v4
the qemu:
https://github.com/lixianglai/qemu
the branch is: interrupt-v3
Please note that the code above is regularly updated based on community
reviews.
change log:
V3->V4:
1.Fix some macro definition names and some formatting errors
2.Combine the IPI two device address Spaces into one address device space
3.Optimize the function kvm_vm_ioctl_irq_line implementation, directly call the public function kvm_set_irq for interrupt distribution
4.Optimize the description of the commit log
5.Deleting an interface trace_kvm_iocsr
V2->V3:
1.Modify the macro definition name:
KVM_DEV_TYPE_LA_* -> KVM_DEV_TYPE_LOONGARCH_*
2.Change the short name for "Extended I/O Interrupt Controller" from EXTIOI to EIOINTC
Rename file extioi.c to eiointc.c
Rename file extioi.h to eiointc.h
V1->V2:
1.Remove redundant blank lines according to community comments
2.Remove simplified redundant code
3.Adds 16 bits of read/write interface to the eiointc iocsr address space
4.Optimize user - and kernel-mode data access interfaces: Access
fixed length data each time to prevent memory overruns
5.Added virtual eiointc, where interrupts can be routed to cpus other than cpu 4
Cc: Bibo Mao <maobibo@...ngson.cn>
Cc: Huacai Chen <chenhuacai@...nel.org>
Cc: kvm@...r.kernel.org
Cc: loongarch@...ts.linux.dev
Cc: Paolo Bonzini <pbonzini@...hat.com>
Cc: Tianrui Zhao <zhaotianrui@...ngson.cn>
Cc: WANG Xuerui <kernel@...0n.name>
Cc: Xianglai li <lixianglai@...ngson.cn>
Xianglai Li (11):
LoongArch: KVM: Add iocsr and mmio bus simulation in kernel
LoongArch: KVM: Add IPI device support
LoongArch: KVM: Add IPI read and write function
LoongArch: KVM: Add IPI user mode read and write function
LoongArch: KVM: Add EIOINTC device support
LoongArch: KVM: Add EIOINTC read and write functions
LoongArch: KVM: Add EIOINTC user mode read and write functions
LoongArch: KVM: Add PCHPIC device support
LoongArch: KVM: Add PCHPIC read and write functions
LoongArch: KVM: Add PCHPIC user mode read and write functions
LoongArch: KVM: Add irqfd support
arch/loongarch/include/asm/kvm_eiointc.h | 122 +++
arch/loongarch/include/asm/kvm_host.h | 18 +-
arch/loongarch/include/asm/kvm_ipi.h | 46 +
arch/loongarch/include/asm/kvm_pch_pic.h | 61 ++
arch/loongarch/include/uapi/asm/kvm.h | 19 +
arch/loongarch/kvm/Kconfig | 5 +-
arch/loongarch/kvm/Makefile | 4 +
arch/loongarch/kvm/exit.c | 80 +-
arch/loongarch/kvm/intc/eiointc.c | 1055 ++++++++++++++++++++++
arch/loongarch/kvm/intc/ipi.c | 468 ++++++++++
arch/loongarch/kvm/intc/pch_pic.c | 523 +++++++++++
arch/loongarch/kvm/irqfd.c | 97 ++
arch/loongarch/kvm/main.c | 19 +-
arch/loongarch/kvm/vcpu.c | 3 +
arch/loongarch/kvm/vm.c | 22 +
include/linux/kvm_host.h | 1 +
include/uapi/linux/kvm.h | 8 +
17 files changed, 2522 insertions(+), 29 deletions(-)
create mode 100644 arch/loongarch/include/asm/kvm_eiointc.h
create mode 100644 arch/loongarch/include/asm/kvm_ipi.h
create mode 100644 arch/loongarch/include/asm/kvm_pch_pic.h
create mode 100644 arch/loongarch/kvm/intc/eiointc.c
create mode 100644 arch/loongarch/kvm/intc/ipi.c
create mode 100644 arch/loongarch/kvm/intc/pch_pic.c
create mode 100644 arch/loongarch/kvm/irqfd.c
base-commit: 906bd684e4b1e517dd424a354744c5b0aebef8af
--
2.39.1
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