linux-kernel - RE: [PATCH v2 03/25] dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator

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Message-ID:
 <TYCPR01MB113327EF54AE67BC77C25F476865F2@TYCPR01MB11332.jpnprd01.prod.outlook.com>
Date: Sun, 10 Nov 2024 08:31:03 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Claudiu.Beznea <claudiu.beznea@...on.dev>, "geert+renesas@...der.be"
	<geert+renesas@...der.be>, "mturquette@...libre.com"
	<mturquette@...libre.com>, "sboyd@...nel.org" <sboyd@...nel.org>,
	"robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org"
	<krzk+dt@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>, Prabhakar
 Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>, "lgirdwood@...il.com"
	<lgirdwood@...il.com>, "broonie@...nel.org" <broonie@...nel.org>,
	"magnus.damm@...il.com" <magnus.damm@...il.com>, "linus.walleij@...aro.org"
	<linus.walleij@...aro.org>, "perex@...ex.cz" <perex@...ex.cz>,
	"tiwai@...e.com" <tiwai@...e.com>, "p.zabel@...gutronix.de"
	<p.zabel@...gutronix.de>
CC: "linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-sound@...r.kernel.org" <linux-sound@...r.kernel.org>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>, Claudiu.Beznea
	<claudiu.beznea@...on.dev>, Claudiu Beznea
	<claudiu.beznea.uj@...renesas.com>, Krzysztof Kozlowski
	<krzysztof.kozlowski@...aro.org>
Subject: RE: [PATCH v2 03/25] dt-bindings: clock: versaclock3: Document
 5L35023 Versa3 clock generator

Hi Claudiu,

Thanks for the patch.

> -----Original Message-----
> From: Claudiu <claudiu.beznea@...on.dev>
> Sent: 08 November 2024 10:50
> Subject: [PATCH v2 03/25] dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator
> 
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> 
> There are some differences b/w 5L35023 and 5P35023 Versa3 clock generator variants but the same driver
> could be used with minimal adjustments. The identified differences are PLL2 Fvco, the clock sel bit
> for SE2 clock and different default values for some registers.
> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>


Reviewed-by: Biju Das <biju.das.jz@...renesas.com>

Cheers,
Biju

> ---
> 
> Changes in v2:
> - collected tags
> 
>  Documentation/devicetree/bindings/clock/renesas,5p35023.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
> b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
> index 42b6f80613f3..162d38035188 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
> @@ -31,6 +31,7 @@ description: |
>  properties:
>    compatible:
>      enum:
> +      - renesas,5l35023
>        - renesas,5p35023
> 
>    reg:
> --
> 2.39.2