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Message-ID: <9c25d4b9-223d-4461-a611-05e65538f4a1@quicinc.com>
Date: Wed, 13 Nov 2024 02:13:08 +0530
From: Akhil P Oommen <quic_akhilpo@...cinc.com>
To: Rob Clark <robdclark@...il.com>, Sean Paul <sean@...rly.run>,
"Konrad
Dybcio" <konradybcio@...nel.org>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Marijn Suijten
<marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, "Simona
Vetter" <simona@...ll.ch>
CC: <linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
<freedreno@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>,
Jie Zhang
<quic_jiezh@...cinc.com>
Subject: Re: [PATCH] drm/msm/a6xx: Add support for Adreno 612
On 11/1/2024 8:40 PM, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@...cinc.com>
>
> Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets.
> A612 falls under ADRENO_6XX_GEN1 family and is a cut down version
> of A615 GPU.
>
> A612 has a new IP called Reduced Graphics Management Unit or RGMU
> which is a small state machine which helps to toggle GX GDSC
> (connected to CX rail) to implement IFPC feature. It doesn't support
> any other features of a full fledged GMU like clock control, resource
> voting to rpmh etc. So we need linux clock driver support like other
> gmu-wrapper implementations to control gpu core clock and gpu GX gdsc.
> Since there is no benefit with enabling RGMU at the moment, RGMU is
> entirely skipped in this patch.
>
> Signed-off-by: Jie Zhang <quic_jiezh@...cinc.com>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@...cinc.com>
> ---
> Mesa support is already available for A612. Verified Glmark2 with
> weston.
>
> Some dependencies for the devicetree change are not yet available
> in the mailing lists. I will send it out as a separate patch later.
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 15 +++++++++++++++
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 28 +++++++++++++++++++++-------
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 ++++++++---
> 3 files changed, 44 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 0c560e84ad5a..234083b69844 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -704,6 +704,21 @@ static const struct adreno_info a6xx_gpus[] = {
> { 157, 3 },
> { 127, 4 },
> ),
> + }, {
> + .chip_ids = ADRENO_CHIP_IDS(0x06010200),
> + .family = ADRENO_6XX_GEN1,
> + .fw = {
> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> + },
> + .gmem = (SZ_128K + SZ_4K),
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a6xx_gpu_init,
> + .a6xx = &(const struct a6xx_info) {
> + .hwcg = a612_hwcg,
> + .protect = &a630_protect,
> + .gmu_cgc_mode = 0x00000022,
> + .prim_fifo_threshold = 0x00080000,
> + },
> }, {
> .chip_ids = ADRENO_CHIP_IDS(0x06010500),
> .family = ADRENO_6XX_GEN1,
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 019610341df1..f69607267262 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -504,15 +504,26 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
>
> if (adreno_is_a630(adreno_gpu))
> clock_cntl_on = 0x8aa8aa02;
> - else if (adreno_is_a610(adreno_gpu))
> + else if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu))
> clock_cntl_on = 0xaaa8aa82;
> else if (adreno_is_a702(adreno_gpu))
> clock_cntl_on = 0xaaaaaa82;
> else
> clock_cntl_on = 0x8aa8aa82;
>
> - cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111;
> - cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555;
> + if (adreno_is_a612(adreno_gpu))
> + cgc_delay = 0x11;
> + else if (adreno_is_a615_family(adreno_gpu))
> + cgc_delay = 0x111;
> + else
> + cgc_delay = 0x10111;
> +
> + if (adreno_is_a612(adreno_gpu))
> + cgc_hyst = 0x55;
> + else if (adreno_is_a615_family(adreno_gpu))
> + cgc_delay = 0x555;
> + else
> + cgc_delay = 0x5555;
>
> gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
> state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
> @@ -600,6 +611,9 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> gpu->ubwc_config.ubwc_swizzle = 0x7;
> }
>
> + if (adreno_is_a612(gpu))
> + gpu->ubwc_config.highest_bank_bit = 13;
> +
> if (adreno_is_a618(gpu))
> gpu->ubwc_config.highest_bank_bit = 14;
>
> @@ -1165,7 +1179,7 @@ static int hw_init(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
>
> /* Setting the mem pool size */
> - if (adreno_is_a610(adreno_gpu)) {
> + if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) {
> gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48);
> gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47);
> } else if (adreno_is_a702(adreno_gpu)) {
> @@ -1199,7 +1213,7 @@ static int hw_init(struct msm_gpu *gpu)
>
> /* Enable fault detection */
> if (adreno_is_a730(adreno_gpu) ||
> - adreno_is_a740_family(adreno_gpu))
> + adreno_is_a740_family(adreno_gpu) || adreno_is_a612(adreno_gpu))
> gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff);
> else if (adreno_is_a690(adreno_gpu))
> gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff);
> @@ -1864,7 +1878,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
> static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
> {
> /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */
> - if (adreno_has_gmu_wrapper(&a6xx_gpu->base))
> + if (adreno_has_gmu_wrapper(&a6xx_gpu->base) && !adreno_is_a612(&a6xx_gpu->base))
> return;
>
> llcc_slice_putd(a6xx_gpu->llc_slice);
> @@ -1877,7 +1891,7 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
> struct device_node *phandle;
>
> /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */
> - if (adreno_has_gmu_wrapper(&a6xx_gpu->base))
> + if (adreno_has_gmu_wrapper(&a6xx_gpu->base) && !adreno_is_a612(&a6xx_gpu->base))
> return;
>
> /*
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index e71f420f8b3a..5cde84817a03 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -420,6 +420,11 @@ static inline int adreno_is_a610(const struct adreno_gpu *gpu)
> return adreno_is_revn(gpu, 610);
> }
>
> +static inline int adreno_is_a612(const struct adreno_gpu *gpu)
> +{
> + return gpu->info->chip_ids[0] == 0x06010200;
> +}
> +
> static inline int adreno_is_a618(const struct adreno_gpu *gpu)
> {
> return adreno_is_revn(gpu, 618);
> @@ -489,9 +494,9 @@ static inline int adreno_is_a610_family(const struct adreno_gpu *gpu)
> {
> if (WARN_ON_ONCE(!gpu->info))
> return false;
> -
> - /* TODO: A612 */
> - return adreno_is_a610(gpu) || adreno_is_a702(gpu);
> + return adreno_is_a610(gpu) ||
> + adreno_is_a702(gpu) ||
> + adreno_is_a612(gpu);
> }
>
> /* TODO: 615/616 */
>
> ---
> base-commit: 4a6fd06643afa99989a0e6b848e125099674227b
> change-id: 20241031-a612-gpu-support-d6330f17d01f
>
> Best regards,
This patch requires a fix up related to llcc. I will send a v2 revision.
-Akhil.
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