linux-kernel - Re: [PATCH v4 8/8] x86/mce: Fix typos

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Message-ID: <befe8002-a5fb-4d68-a7f6-1bffb97ed255@intel.com>
Date: Tue, 12 Nov 2024 14:35:32 -0800
From: Sohil Mehta <sohil.mehta@...el.com>
To: Yazen Ghannam <yazen.ghannam@....com>, Qiuxu Zhuo <qiuxu.zhuo@...el.com>
CC: <bp@...en8.de>, <tony.luck@...el.com>, <tglx@...utronix.de>,
	<dave.hansen@...ux.intel.com>, <mingo@...hat.com>, <hpa@...or.com>,
	<nik.borisov@...e.com>, <x86@...nel.org>, <linux-edac@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 8/8] x86/mce: Fix typos

On 11/12/2024 7:38 AM, Yazen Ghannam wrote:
> 
>>  		 * This way when there are any shared banks it will be
>>  		 * only seen by one CPU before cleared, avoiding duplicates.
>>  		 */
>> @@ -1917,7 +1917,7 @@ static void apply_quirks_amd(struct cpuinfo_x86 *c)
>>  	/* This should be disabled by the BIOS, but isn't always */
>>  	if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
>>  		/*
>> -		 * disable GART TBL walk error reporting, which
>> +		 * disable GART TLB walk error reporting, which
> 
> This also is not a typo. TBL -> table
> 
> From old AMD K8 BKDG document:
> 	10 GartTblWkEn GART Table Walk Error Reporting Enable R/W 0
> 

There is another comment in init_amd_gh() that seems to be related to
the same thing and similarly worded. That seems to refer to TLB instead
of TBL(table).

/*
 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
 * is always needed when GART is enabled, even in a kernel which has no
 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
 * If it doesn't, we do it here as suggested by the BKDG.
 *
 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
 */
msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);