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Message-ID: <20241112003015.qxuufx6jrfeoqfak@jpoimboe>
Date: Mon, 11 Nov 2024 16:30:15 -0800
From: Josh Poimboeuf <jpoimboe@...nel.org>
To: "Kaplan, David" <David.Kaplan@....com>
Cc: Amit Shah <amit@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
"x86@...nel.org" <x86@...nel.org>,
"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
"Shah, Amit" <Amit.Shah@....com>,
"Lendacky, Thomas" <Thomas.Lendacky@....com>,
"bp@...en8.de" <bp@...en8.de>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"peterz@...radead.org" <peterz@...radead.org>,
"pawan.kumar.gupta@...ux.intel.com" <pawan.kumar.gupta@...ux.intel.com>,
"corbet@....net" <corbet@....net>,
"mingo@...hat.com" <mingo@...hat.com>,
"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
"hpa@...or.com" <hpa@...or.com>,
"seanjc@...gle.com" <seanjc@...gle.com>,
"pbonzini@...hat.com" <pbonzini@...hat.com>,
"daniel.sneddon@...ux.intel.com" <daniel.sneddon@...ux.intel.com>,
"kai.huang@...el.com" <kai.huang@...el.com>,
"Das1, Sandipan" <Sandipan.Das@....com>,
"boris.ostrovsky@...cle.com" <boris.ostrovsky@...cle.com>,
"Moger, Babu" <Babu.Moger@....com>,
"dwmw@...zon.co.uk" <dwmw@...zon.co.uk>,
"andrew.cooper3@...rix.com" <andrew.cooper3@...rix.com>
Subject: Re: [RFC PATCH v2 1/3] x86: cpu/bugs: update SpectreRSB comments for
AMD
On Mon, Nov 11, 2024 at 12:40:41PM -0800, Josh Poimboeuf wrote:
> On Mon, Nov 11, 2024 at 12:39:09PM -0800, Josh Poimboeuf wrote:
> > This is why it's important to spell out all the different cases in the
> > comments. I was attempting to document the justifications for the
> > existing behavior.
> >
> > You make some good points, though backing up a bit, I realize my comment
> > was flawed for another reason: the return thunks only protect the
> > kernel, but RSB filling on context switch is meant to protect user
> > space.
> >
> > So, never mind...
>
> That said, I still think the comments need an update. I'll try to come
> up with something later.
Here are some clarifications to the comments. Amit, feel free to
include this in your next revision.
----8<----
From: Josh Poimboeuf <jpoimboe@...nel.org>
Subject: [PATCH] x86/bugs: Update insanely long comment about RSB attacks
The long comment above the setting of X86_FEATURE_RSB_CTXSW is a bit
confusing. It starts out being about context switching specifically,
but then goes on to describe "user -> kernel" mitigations, which aren't
necessarily limited to context switches.
Clarify that it's about *all* RSB attacks and their mitigations.
For consistency, add the "guest -> host" mitigations as well. Then the
comment above spectre_v2_determine_rsb_fill_type_at_vmexit() can be
removed and the overall line count is reduced.
Signed-off-by: Josh Poimboeuf <jpoimboe@...nel.org>
---
arch/x86/kernel/cpu/bugs.c | 59 ++++++++++++--------------------------
1 file changed, 19 insertions(+), 40 deletions(-)
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 47a01d4028f6..fbdfa151b7a9 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -1581,26 +1581,6 @@ static void __init spec_ctrl_disable_kernel_rrsba(void)
static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)
{
- /*
- * Similar to context switches, there are two types of RSB attacks
- * after VM exit:
- *
- * 1) RSB underflow
- *
- * 2) Poisoned RSB entry
- *
- * When retpoline is enabled, both are mitigated by filling/clearing
- * the RSB.
- *
- * When IBRS is enabled, while #1 would be mitigated by the IBRS branch
- * prediction isolation protections, RSB still needs to be cleared
- * because of #2. Note that SMEP provides no protection here, unlike
- * user-space-poisoned RSB entries.
- *
- * eIBRS should protect against RSB poisoning, but if the EIBRS_PBRSB
- * bug is present then a LITE version of RSB protection is required,
- * just a single call needs to retire before a RET is executed.
- */
switch (mode) {
case SPECTRE_V2_NONE:
return;
@@ -1818,43 +1798,42 @@ static void __init spectre_v2_select_mitigation(void)
pr_info("%s\n", spectre_v2_strings[mode]);
/*
- * If Spectre v2 protection has been enabled, fill the RSB during a
- * context switch. In general there are two types of RSB attacks
- * across context switches, for which the CALLs/RETs may be unbalanced.
+ * In general there are two types of RSB attacks:
*
- * 1) RSB underflow
+ * 1) RSB underflow ("Intel Retbleed")
*
* Some Intel parts have "bottomless RSB". When the RSB is empty,
* speculated return targets may come from the branch predictor,
* which could have a user-poisoned BTB or BHB entry.
*
- * AMD has it even worse: *all* returns are speculated from the BTB,
- * regardless of the state of the RSB.
+ * When IBRS or eIBRS is enabled, the "user -> kernel" attack is
+ * mitigated by the IBRS branch prediction isolation properties, so
+ * the RSB buffer filling wouldn't be necessary to protect against
+ * this type of attack.
*
- * When IBRS or eIBRS is enabled, the "user -> kernel" attack
- * scenario is mitigated by the IBRS branch prediction isolation
- * properties, so the RSB buffer filling wouldn't be necessary to
- * protect against this type of attack.
+ * The "user -> user" attack is mitigated by RSB filling on context
+ * switch.
*
- * The "user -> user" attack scenario is mitigated by RSB filling.
+ * The "guest -> host" attack is mitigated by IBRS or eIBRS.
*
* 2) Poisoned RSB entry
*
* If the 'next' in-kernel return stack is shorter than 'prev',
* 'next' could be tricked into speculating with a user-poisoned RSB
- * entry.
+ * entry. Speculative Type Confusion ("AMD retbleed") can also
+ * create poisoned RSB entries.
*
- * The "user -> kernel" attack scenario is mitigated by SMEP and
- * eIBRS.
+ * The "user -> kernel" attack is mitigated by SMEP and eIBRS.
*
- * The "user -> user" scenario, also known as SpectreBHB, requires
- * RSB clearing.
+ * The "user -> user" attack, also known as SpectreBHB, requires RSB
+ * clearing.
*
- * So to mitigate all cases, unconditionally fill RSB on context
- * switches.
- *
- * FIXME: Is this pointless for retbleed-affected AMD?
+ * The "guest -> host" attack is mitigated by eIBRS (not IBRS!) or
+ * RSB clearing on vmexit. Note that eIBRS implementations with
+ * X86_BUG_EIBRS_PBRSB still need "lite" RSB clearing which retires
+ * a single CALL before the first RET.
*/
+
setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
--
2.47.0
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