[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <20241112075826.28296-1-quic_rlaggysh@quicinc.com>
Date: Tue, 12 Nov 2024 07:58:23 +0000
From: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
To: Georgi Djakov <djakov@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konradybcio@...nel.org>
CC: Sibi Sankar <quic_sibis@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<linux-pm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
Odelu Kukatla <quic_okukatla@...cinc.com>,
Mike Tipton <quic_mdtipton@...cinc.com>
Subject: [PATCH V4 0/3] Add EPSS L3 provider support on SA8775P SoC
Add Epoch Subsystem (EPSS) L3 provider support on SA8775P SoCs.
Changes since v3:
- Removed epss-l3-perf generic compatible changes. These will be posted
as separate patch until then SoC specific compatible will be used for
probing.
Changes since v2:
- Updated the commit text to reflect the reason for code change.
- Added SoC-specific and generic compatible to driver match table.
Changes since v1:
- Removed the usage of static IDs and implemented dynamic ID assignment
for icc nodes using IDA.
- Removed separate compatibles for cl0 and cl1. Both cl0 and cl1
devices use the same compatible.
- Added new generic compatible for epss-l3-perf.
Raviteja Laggyshetty (3):
dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P
arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider
interconnect: qcom: Add EPSS L3 support on SA8775P
.../bindings/interconnect/qcom,osm-l3.yaml | 1 +
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 ++++
drivers/interconnect/qcom/osm-l3.c | 86 ++++++++++++++-----
3 files changed, 84 insertions(+), 22 deletions(-)
--
2.39.2
Powered by blists - more mailing lists