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Message-ID:
<AS8PR04MB86761D45F67FC31602F45ABB8C592@AS8PR04MB8676.eurprd04.prod.outlook.com>
Date: Tue, 12 Nov 2024 09:00:24 +0000
From: Hongxing Zhu <hongxing.zhu@....com>
To: Frank Li <frank.li@....com>, Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org>
CC: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>, Bjorn Helgaas
<helgaas@...nel.org>, "jingoohan1@...il.com" <jingoohan1@...il.com>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>, "lpieralisi@...nel.org"
<lpieralisi@...nel.org>, "kw@...ux.com" <kw@...ux.com>, "robh@...nel.org"
<robh@...nel.org>, "imx@...ts.linux.dev" <imx@...ts.linux.dev>,
"kernel@...gutronix.de" <kernel@...gutronix.de>, "linux-pci@...r.kernel.org"
<linux-pci@...r.kernel.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v1] PCI: dwc: Clean up some unnecessary codes in
dw_pcie_suspend_noirq()
> -----Original Message-----
> From: Frank Li <frank.li@....com>
> Sent: 2024年11月12日 0:18
> To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> Cc: Hongxing Zhu <hongxing.zhu@....com>; Krishna Chaitanya Chundru
> <quic_krichai@...cinc.com>; Bjorn Helgaas <helgaas@...nel.org>;
> jingoohan1@...il.com; bhelgaas@...gle.com; lpieralisi@...nel.org;
> kw@...ux.com; robh@...nel.org; imx@...ts.linux.dev;
> kernel@...gutronix.de; linux-pci@...r.kernel.org;
> linux-kernel@...r.kernel.org
> Subject: Re: [PATCH v1] PCI: dwc: Clean up some unnecessary codes in
> dw_pcie_suspend_noirq()
>
> On Mon, Nov 11, 2024 at 11:03:22AM +0530, Manivannan Sadhasivam wrote:
> > On Mon, Nov 11, 2024 at 03:29:18AM +0000, Hongxing Zhu wrote:
> > > > -----Original Message-----
> > > > From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
> > > > Sent: 2024年11月10日 8:10
> > > > To: Bjorn Helgaas <helgaas@...nel.org>; Manivannan Sadhasivam
> > > > <manivannan.sadhasivam@...aro.org>
> > > > Cc: Hongxing Zhu <hongxing.zhu@....com>; jingoohan1@...il.com;
> > > > bhelgaas@...gle.com; lpieralisi@...nel.org; kw@...ux.com;
> > > > robh@...nel.org; Frank Li <frank.li@....com>; imx@...ts.linux.dev;
> > > > kernel@...gutronix.de; linux-pci@...r.kernel.org;
> > > > linux-kernel@...r.kernel.org
> > > > Subject: Re: [PATCH v1] PCI: dwc: Clean up some unnecessary codes
> > > > in
> > > > dw_pcie_suspend_noirq()
> > > >
> > > >
> > > >
> > > > On 11/8/2024 5:54 AM, Bjorn Helgaas wrote:
> > > > > On Thu, Nov 07, 2024 at 11:13:34AM +0000, Manivannan Sadhasivam
> > > > wrote:
> > > > >> On Thu, Nov 07, 2024 at 04:44:55PM +0800, Richard Zhu wrote:
> > > > >>> Before sending PME_TURN_OFF, don't test the LTSSM stat. Since
> > > > >>> it's safe to send PME_TURN_OFF message regardless of whether
> > > > >>> the link is up or down. So, there would be no need to test the
> > > > >>> LTSSM stat before sending PME_TURN_OFF message.
> > > > >>
> > > > >> What is the incentive to send PME_Turn_Off when link is not up?
> > > > >
> > > > > There's no need to send PME_Turn_Off when link is not up.
> > > > >
> > > > > But a link-up check is inherently racy because the link may go
> > > > > down between the check and the PME_Turn_Off. Since it's
> > > > > impossible for software to guarantee the link is up, the Root
> > > > > Port should be able to tolerate attempts to send PME_Turn_Off when
> the link is down.
> > > > >
> > > > > So IMO there's no need to check whether the link is up, and
> > > > > checking gives the misleading impression that "we know the link
> > > > > is up and therefore sending PME_Turn_Off is safe."
> > > > >
> > > > Hi Bjorn,
> > > >
> > > > I agree that link-up check is racy but once link is up and link
> > > > has gone down due to some reason the ltssm state will not move
> > > > detect quiet or detect act, it will go to pre detect quiet (i.e value 0f 0x5).
> > > > we can assume if the link is up LTSSM state will greater than
> > > > detect act even if the link was down.
> > > >
> > > > - Krishna Chaitanya.
> > > > >>> Remove the L2 poll too, after the PME_TURN_OFF message is sent
> out.
> > > > >>> Because the re-initialization would be done in
> > > > >>> dw_pcie_resume_noirq().
> > > > >>
> > > > >> As Krishna explained, host needs to wait until the endpoint
> > > > >> acks the message (just to give it some time to do cleanups).
> > > > >> Then only the host can initiate D3Cold. It matters when the device
> supports L2.
> > > > >
> > > > > The important thing here is to be clear about the *reason* to
> > > > > poll for
> > > > > L2 and the *event* that must wait for L2.
> > > > >
> > > > > I don't have any DesignWare specs, but when
> > > > > dw_pcie_suspend_noirq() waits for DW_PCIE_LTSSM_L2_IDLE, I think
> > > > > what we're doing is waiting for the link to be in the L2/L3
> > > > > Ready pseudo-state (PCIe r6.0, sec 5.2, fig 5-1).
> > > > >
> > > > > L2 and L3 are states where main power to the downstream
> > > > > component is off, i.e., the component is in D3cold (r6.0, sec
> > > > > 5.3.2), so there is no link in those states.
> > > > >
> > > > > The PME_Turn_Off handshake is part of the process to put the
> > > > > downstream component in D3cold. I think the reason for this
> > > > > handshake is to allow an orderly shutdown of that component
> > > > > before main power is removed.
> > > > >
> > > > > When the downstream component receives PME_Turn_Off, it will
> > > > > stop scheduling new TLPs, but it may already have TLPs scheduled
> > > > > but not yet sent. If power were removed immediately, they would
> > > > > be lost. My understanding is that the link will not enter L2/L3
> > > > > Ready until the components on both ends have completed whatever
> > > > > needs to be done with those TLPs. (This is based on the L2/L3
> > > > > discussion in the Mindshare PCIe book; I haven't found clear
> > > > > spec citations for all of it.)
> > > > >
> > > > > I think waiting for L2/L3 Ready is to keep us from turning off
> > > > > main power when the components are still trying to dispose of those
> TLPs.
> > > > >
> > > > > So I think every controller that turns off main power needs to
> > > > > wait for L2/L3 Ready.
> > > > >
> > > > > There's also a requirement that software wait at least 100 ns
> > > > > after
> > > > > L2/L3 Ready before turning off refclock and main power (sec
> > > > > 5.3.3.2.1).
> > > Thanks for the comments.
> > > So, the L2 poll is better kept, since PCIe r6.0, sec 5.3.3.2.1 also
> > > recommends 1ms to 10ms timeout to check L2 ready or not.
> > > The v2 of this patch would only remove the LTSSM stat check when
> > > issue the PME_TURN_OFF message if there are no further comments.
> > >
> >
> > If you unconditionally send PME_Turn_Off message, then you'd end up
> > polling for
> > L23 Ready, which may result in a timeout and users will see the error
> message.
> > This is my concern.
>
> Yes, may we can check if entry L2 or link down, so no such message print for
> link down case.
>
At the L2/L3 Ready wait moment, the link should be still up stat, right?
Before dump the error message, how about to check link is up or not like this:
ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,
PCIE_PME_TO_L2_TIMEOUT_US/10,
PCIE_PME_TO_L2_TIMEOUT_US, false, pci);
- if (ret) {
+ if (ret && dw_pcie_link_up(pci)) {
dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);
return ret;
}
Best Regards
Richard Zhu
> Frank
>
> >
> > - Mani
> >
> > --
> > மணிவண்ணன் சதாசிவம்
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