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Message-ID: <20241113020233.3646527-1-ragavendra.bn@gmail.com>
Date: Tue, 12 Nov 2024 18:02:33 -0800
From: Ragavendra <ragavendra.bn@...il.com>
To: mturquette@...libre.com,
sboyd@...nel.org,
unicorn_wang@...look.com,
inochiama@...look.com
Cc: linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org,
Ragavendra <ragavendra.bn@...il.com>
Subject: [PATCH] clk:sophgo:clk-cv18xx-pll: fix unitialized u32 variable
Initializing the val variable of type u32 as it was not initialized.
Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
Signed-off-by: Ragavendra Nagraj <ragavendra.bn@...il.com>
---
drivers/clk/sophgo/clk-cv18xx-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c
index 29e24098bf5f..04a0419cab4e 100644
--- a/drivers/clk/sophgo/clk-cv18xx-pll.c
+++ b/drivers/clk/sophgo/clk-cv18xx-pll.c
@@ -87,7 +87,7 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,
static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
- u32 val;
+ u32 val = 0;
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
return ipll_find_rate(pll->pll_limit, req->best_parent_rate,
--
2.46.1
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