From fa351c7614dd97713b26342c96c61fc28699d8d4 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 13 Nov 2024 17:14:10 +0100 Subject: [PATCH] platform/x86: p2sb: Cache correct PCI bar for P2SB on Denverton and Gemini Lake Denverton and Gemini Lak are Goldmont derived designs and as such have the P2SB at device.function 13.0, rather then at the default 31.1. At a mapping to P2SB_DEVFN_GOLDMONT to p2sb_cpu_ids[] for these 2 Goldmont variants so that the correct PCI bar gets cached. This fixes P2SB unhiding not working on these devices which fixes GPIO and SPI (Gemini Lake only) support not working on devices where these were hidden by the BIOS. Fixes: 2841631a0365 ("platform/x86: p2sb: Allow p2sb_bar() calls during PCI device probe") Reported-by: Daniel Walker (danielwa) Closes: https://lore.kernel.org/lkml/ZzTI+biIUTvFT6NC@goliath/ Signed-off-by: Hans de Goede --- drivers/platform/x86/p2sb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/platform/x86/p2sb.c b/drivers/platform/x86/p2sb.c index 31f38309b389..beb94c492eec 100644 --- a/drivers/platform/x86/p2sb.c +++ b/drivers/platform/x86/p2sb.c @@ -25,6 +25,8 @@ static const struct x86_cpu_id p2sb_cpu_ids[] = { X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, P2SB_DEVFN_GOLDMONT), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, P2SB_DEVFN_GOLDMONT), {} }; -- 2.47.0