linux-kernel - Re: [PATCH v2 1/2] dt-bindings: phy: Add Rockchip MIPI CSI/DSI PHY schema

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Message-ID: <18621846.sWSEgdgrri@diego>
Date: Wed, 13 Nov 2024 19:50:33 +0100
From: Heiko Stübner <heiko@...ech.de>
To: vkoul@...nel.org, kishon@...nel.org,
 Diederik de Haas <didi.debian@...ow.org>
Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
 quentin.schulz@...rry.de, linux-phy@...ts.infradead.org,
 devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
 Heiko Stuebner <heiko.stuebner@...rry.de>
Subject:
 Re: [PATCH v2 1/2] dt-bindings: phy: Add Rockchip MIPI CSI/DSI PHY schema

Hi,

Am Mittwoch, 6. November 2024, 15:17:02 CET schrieb Diederik de Haas:
> On Mon Nov 4, 2024 at 12:11 PM CET, Heiko Stuebner wrote:
> > From: Heiko Stuebner <heiko.stuebner@...rry.de>
> >
> > Add dt-binding schema for the MIPI CSI/DSI PHY found on
> > Rockchip RK3588 SoCs.
> >
> > Signed-off-by: Heiko Stuebner <heiko.stuebner@...rry.de>
> > ---
> >  .../phy/rockchip,rk3588-mipi-dcphy.yaml       | 82 +++++++++++++++++++
> >  1 file changed, 82 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml
> > new file mode 100644
> > index 000000000000..5ee8d7246fa0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml
> > @@ -0,0 +1,82 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/rockchip,rk3588-mipi-dcphy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Rockchip MIPI CSI/DSI PHY with Samsung IP block
> > +
> > +maintainers:
> > +  - Guochun Huang <hero.huang@...k-chips.com>
> > +  - Heiko Stuebner <heiko@...ech.de>
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - rockchip,rk3576-mipi-dcphy
> > +      - rockchip,rk3588-mipi-dcphy
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  "#phy-cells":
> > +    const: 0
> > +
> > +  clocks:
> > +    maxItems: 2
> > +
> > +  clock-names:
> > +    items:
> > +      - const: pclk
> > +      - const: ref
> > +
> > +  resets:
> > +    maxItems: 4
> > +
> > +  reset-names:
> > +    items:
> > +      - const: m_phy
> > +      - const: apb
> > +      - const: grf
> > +      - const: s_phy
> > +
> > +  rockchip,grf:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description:
> > +      Phandle to the syscon managing the 'mipi dcphy general register files'.
> 
> Should this dt-binding have a power-domains property?
> RK3588 TRM v1.0 part 1 page 1097 has ALIVE(PD_BUS) for
> MIPI_DC_PHY0~MIPI_DC_PHY1

I don't think so. As you write, the dcphy is part of the PD_BUS(ALIVE)
power-domain on at least rk3588 and the new rk3576.

This power-domain is actually non-controllable and also contains things
like the main GIC - so will be always on.

And for that reason probably, that domain also is not even exposed
in the rk3588 devicetree (nor the driver implementation).

Similarly the hdptx phy binding (in a similar situation) also does not
handle a power-domain. So my thinking is, we'll stay like this for now.


Heiko

> FTR: I made a similar remark on another patch sent by Heiko today. While
> that was incorrect, I do think it's appropriate for this binding after
> which it could also be added to the respective phy nodes in the dts(i)
> file(s).
> 
> Cheers,
>   Diederik
> 
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - resets
> > +  - reset-names
> > +  - "#phy-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
> > +    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
> > +
> > +    soc {
> > +      #address-cells = <2>;
> > +      #size-cells = <2>;
> > +
> > +      phy@...a0000 {
> > +        compatible = "rockchip,rk3588-mipi-dcphy";
> > +        reg = <0x0 0xfeda0000 0x0 0x10000>;
> > +        clocks = <&cru PCLK_MIPI_DCPHY0>,
> > +                 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
> > +        clock-names = "pclk", "ref";
> > +        resets = <&cru SRST_M_MIPI_DCPHY0>,
> > +                 <&cru SRST_P_MIPI_DCPHY0>,
> > +                 <&cru SRST_P_MIPI_DCPHY0_GRF>,
> > +                 <&cru SRST_S_MIPI_DCPHY0>;
> > +        reset-names = "m_phy", "apb", "grf", "s_phy";
> > +        rockchip,grf = <&mipidcphy0_grf>;
> > +        #phy-cells = <0>;
> > +      };
> > +    };
> 
>