linux-kernel - Re: [PATCH v10 02/10] iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is not supported

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <558bf28e-6cf8-436d-b2ef-382ff421bb00@app.fastmail.com>
Date: Wed, 13 Nov 2024 13:35:10 +0100
From: "Arnd Bergmann" <arnd@...db.de>
To: "Suravee Suthikulpanit" <suravee.suthikulpanit@....com>,
 linux-kernel@...r.kernel.org, iommu@...ts.linux.dev
Cc: "Joerg Roedel" <joro@...tes.org>, "Robin Murphy" <robin.murphy@....com>,
 vasant.hegde@....com, "Uros Bizjak" <ubizjak@...il.com>,
 Linux-Arch <linux-arch@...r.kernel.org>, "Jason Gunthorpe" <jgg@...dia.com>,
 "Kevin Tian" <kevin.tian@...el.com>, jon.grimm@....com,
 santosh.shukla@....com, pandoh@...gle.com, kumaranand@...gle.com
Subject: Re: [PATCH v10 02/10] iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is
 not supported

On Wed, Nov 13, 2024, at 13:03, Suravee Suthikulpanit wrote:
> According to the AMD IOMMU spec, IOMMU hardware reads the entire DTE
> in a single 256-bit transaction. It is recommended to update DTE using
> 128-bit operation followed by an INVALIDATE_DEVTAB_ENTYRY command when
> the IV=1b or V=1b before the change.
>
> According to the AMD BIOS and Kernel Developer's Guide (BDKG) dated back
> to family 10h Processor [1], which is the first introduction of AMD IOMMU,
> AMD processor always has CPUID Fn0000_0001_ECX[CMPXCHG16B]=1.
> Therefore, it is safe to assume cmpxchg128 is available with all AMD
> processor w/ IOMMU.

Makes sense. More specifically, I'm fairly sure the only x86-64
CPUs without cmpxchg16b are very early NetBurst Xeons, while AMD
had the instruction from the start, and dropping the runtime check
entirely would work just as well.

      Arnd