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Message-ID: <185be5a4-7bc7-41c1-bdfb-5384fd307a15@asahilina.net>
Date: Thu, 14 Nov 2024 00:17:21 +0900
From: Asahi Lina <lina@...hilina.net>
To: Miklos Szeredi <miklos@...redi.hu>
Cc: Dan Williams <dan.j.williams@...el.com>, Jan Kara <jack@...e.cz>,
Alexander Viro <viro@...iv.linux.org.uk>,
Christian Brauner <brauner@...nel.org>, Matthew Wilcox
<willy@...radead.org>, Sergio Lopez Pascual <slp@...hat.com>,
asahi@...ts.linux.dev, linux-fsdevel@...r.kernel.org,
linux-kernel@...r.kernel.org, Vivek Goyal <vgoyal@...hat.com>
Subject: Re: [PATCH] fuse: dax: No-op writepages callback
On 11/13/24 7:48 PM, Miklos Szeredi wrote:
> On Tue, 12 Nov 2024 at 20:55, Asahi Lina <lina@...hilina.net> wrote:
>>
>> When using FUSE DAX with virtiofs, cache coherency is managed by the
>> host. Disk persistence is handled via fsync() and friends, which are
>> passed directly via the FUSE layer to the host. Therefore, there's no
>> need to do dax_writeback_mapping_range(). All that ends up doing is a
>> cache flush operation, which is not caught by KVM and doesn't do much,
>> since the host and guest are already cache-coherent.
>
> The conclusion seems convincing. But adding Vivek, who originally
> added this in commit 9483e7d5809a ("virtiofs: define dax address space
> operations").
>
> What I'm not clearly seeing is how virtually aliased CPU caches
> interact with this. In mm/filemap.c I see the flush_dcache_folio()
> calls which deal with the kernel mapping of a page being in a
> different cacheline as the user mapping. How does that work in the
> virt environment?
>
Oof, I forgot those architectures existed...
The only architecture that has both a KVM implementation and selects
ARCH_HAS_CPU_CACHE_ALIASING is mips. Is it possible that no MIPS
implementations with virtualization also have cache aliasing, and we can
just not care about this?
~~ Lina
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