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Message-ID: <pcubmgfl2afe5qt5jkvmym5j7o2qabablaqckviu4buneph745@b3s574jztqcb>
Date: Thu, 14 Nov 2024 14:07:20 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Soutrik Mukhopadhyay <quic_mukhopad@...cinc.com>
Cc: andersson@...nel.org, konradybcio@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, quic_riteshk@...cinc.com,
quic_vproddut@...cinc.com, quic_abhinavk@...cinc.com
Subject: Re: [PATCH v3 1/2] arm64: dts: qcom: sa8775p: add DisplayPort device
nodes
On Thu, Nov 14, 2024 at 03:24:59PM +0530, Soutrik Mukhopadhyay wrote:
> Add device tree nodes for the DPTX0 and DPTX1 controllers
> with their corresponding PHYs found on Qualcomm SA8775P SoC.
>
> Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@...cinc.com>
This most likely wasn't validated against DT schema. Please don't send
unvalidated DT patches.
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 216 +++++++++++++++++++++++++-
> 1 file changed, 215 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index f7a9d1684a79..b272feae8da1 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -3343,6 +3343,25 @@
> interrupt-parent = <&mdss0>;
> interrupts = <0>;
>
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf0_out: endpoint {
> + remote-endpoint = <&mdss0_dp0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dpu_intf4_out: endpoint {
> + remote-endpoint = <&mdss0_dp1_in>;
> + };
> + };
> + };
> +
> mdss0_mdp_opp_table: opp-table {
> compatible = "operating-points-v2";
>
> @@ -3367,6 +3386,200 @@
> };
> };
> };
> +
> + mdss0_dp0_phy: phy@...2a00 {
> + compatible = "qcom,sa8775p-edp-phy";
> +
> + reg = <0x0 0xaec2a00 0x0 0x200>,
> + <0x0 0xaec2200 0x0 0xd0>,
> + <0x0 0xaec2600 0x0 0xd0>,
> + <0x0 0xaec2000 0x0 0x1c8>;
> +
> + clocks =<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
> + clock-names = "aux",
> + "cfg_ahb";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + mdss0_dp1_phy: phy@...5a00 {
> + compatible = "qcom,sa8775p-edp-phy";
> +
> + reg = <0x0 0xaec5a00 0x0 0x200>,
> + <0x0 0xaec5200 0x0 0xd0>,
> + <0x0 0xaec5600 0x0 0xd0>,
> + <0x0 0xaec5000 0x0 0x1c8>;
> +
> + clocks =<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
> + clock-names = "aux",
> + "cfg_ahb";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + mdss0_dp0: displayport-controller@...4000 {
> + compatible = "qcom,sa8775p-dp";
> +
> + reg = <0x0 0xaf54000 0x0 0x104>,
> + <0x0 0xaf54200 0x0 0x0c0>,
> + <0x0 0xaf55000 0x0 0x770>,
> + <0x0 0xaf56000 0x0 0x09c>;
No p1 region?
> +
> + interrupt-parent = <&mdss0>;
> + interrupts = <12>;
> +
> + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel";
> + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
> + phys = <&mdss0_dp0_phy>;
> + phy-names = "dp";
> +
> + operating-points-v2 = <&dp_opp_table>;
> + power-domains = <&rpmhpd SA8775P_MMCX>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + mdss0_dp0_in: endpoint {
> + remote-endpoint = <&dpu_intf0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mdss0_dp0_out: endpoint { };
> + };
> + };
> +
> + dp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + mdss0_dp1: displayport-controller@...c000 {
> + compatible = "qcom,sa8775p-dp";
> +
> + reg = <0x0 0xaf5c000 0x0 0x104>,
> + <0x0 0xaf5c200 0x0 0x0c0>,
> + <0x0 0xaf5d000 0x0 0x770>,
> + <0x0 0xaf5e000 0x0 0x09c>;
> +
> + interrupt-parent = <&mdss0>;
> + interrupts = <13>;
> +
> + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel";
> + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
> + phys = <&mdss0_dp1_phy>;
> + phy-names = "dp";
> +
> + operating-points-v2 = <&dp1_opp_table>;
> + power-domains = <&rpmhpd SA8775P_MMCX>;
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + mdss0_dp1_in: endpoint {
> + remote-endpoint = <&dpu_intf4_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mdss0_dp1_out: endpoint { };
> + };
> + };
> +
> + dp1_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> };
>
> dispcc0: clock-controller@...0000 {
> @@ -3376,7 +3589,8 @@
> <&rpmhcc RPMH_CXO_CLK>,
> <&rpmhcc RPMH_CXO_CLK_A>,
> <&sleep_clk>,
> - <0>, <0>, <0>, <0>,
> + <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
> + <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
> <0>, <0>, <0>, <0>;
> power-domains = <&rpmhpd SA8775P_MMCX>;
> #clock-cells = <1>;
> --
> 2.17.1
>
--
With best wishes
Dmitry
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