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Message-ID: <ec66b579-90b7-42cc-b4d4-f4c2e906aeb9@molgen.mpg.de>
Date: Thu, 14 Nov 2024 15:02:49 +0100
From: Paul Menzel <pmenzel@...gen.mpg.de>
To: Tore Amundsen <tore@...ndsen.org>
Cc: netdev@...r.kernel.org, Tony Nguyen <anthony.l.nguyen@...el.com>,
Przemek Kitszel <przemyslaw.kitszel@...el.com>,
Andrew Lunn <andrew+netdev@...n.ch>, "David S . Miller"
<davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
intel-wired-lan@...ts.osuosl.org, linux-kernel@...r.kernel.org,
Ernesto Castellotti <ernesto@...tellotti.net>
Subject: Re: [Intel-wired-lan] [PATCH 1/1] ixgbe: Correct BASE-BX10 compliance
code
[Cc: +Ernesto]
Dear Tore,
Thank you for your patch.
Am 10.11.24 um 00:25 schrieb Tore Amundsen:
> SFF-8472 (section 5.4 Transceiver Compliance Codes) defines bit 6 as
> BASE-BX10. Bit 6 means a value of 0x40 (decimal 64).
>
> The current value in the source code is 0x64, which appears to be a
> mix-up of hex and decimal values. A value of 0x64 (binary 01100100)
> incorrectly sets bit 2 (1000BASE-CX) and bit 5 (100BASE-FX) as well.
>
> Signed-off-by: Tore Amundsen <tore@...ndsen.org>
Could you add a Fixes: tag?
Fixes: 1b43e0d20f2d (ixgbe: Add 1000BASE-BX support)
> ---
> drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
> index 14aa2ca51f70..81179c60af4e 100644
> --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
> @@ -40,7 +40,7 @@
> #define IXGBE_SFF_1GBASESX_CAPABLE 0x1
> #define IXGBE_SFF_1GBASELX_CAPABLE 0x2
> #define IXGBE_SFF_1GBASET_CAPABLE 0x8
> -#define IXGBE_SFF_BASEBX10_CAPABLE 0x64
> +#define IXGBE_SFF_BASEBX10_CAPABLE 0x40
> #define IXGBE_SFF_10GBASESR_CAPABLE 0x10
> #define IXGBE_SFF_10GBASELR_CAPABLE 0x20
> #define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8
Reviewed-by: Paul Menzel <pmenzel@...gen.mpg.de>
Kind regards,
Paul
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