linux-kernel - Re: [PATCH v2 3/6] arm64: dts: qcom: Add base SM8750 dtsi

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Message-ID: <636c2392-bcd6-45ae-a7f7-ed893479d3dd@oss.qualcomm.com>
Date: Fri, 15 Nov 2024 21:26:03 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Melody Olvera <quic_molvera@...cinc.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
 <conor+dt@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        Neil Armstrong <neil.armstrong@...aro.org>,
        Arnd Bergmann <arnd@...db.de>,
        Nícolas F . R . A . Prado <nfraprado@...labora.com>,
        Trilok Soni <quic_tsoni@...cinc.com>,
        Satya Durga Srinivasu Prabhala <quic_satyap@...cinc.com>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Taniya Das <quic_tdas@...cinc.com>,
        Jishnu Prakash <quic_jprakash@...cinc.com>,
        Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
Subject: Re: [PATCH v2 3/6] arm64: dts: qcom: Add base SM8750 dtsi

On 12.11.2024 1:49 AM, Melody Olvera wrote:
> Add the base dtsi for the SM8750 SoC describing the CPUs, GCC and
> RPMHCC clock controllers, geni UART, interrupt controller, TLMM,
> reserved memory, interconnects, and SMMU.
> 
> Co-developed-by: Taniya Das <quic_tdas@...cinc.com>
> Signed-off-by: Taniya Das <quic_tdas@...cinc.com>
> Co-developed-by: Jishnu Prakash <quic_jprakash@...cinc.com>
> Signed-off-by: Jishnu Prakash <quic_jprakash@...cinc.com>
> Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@...cinc.com>
> ---

[...]

> +			power-domain-names = "psci";
> +			cpu-idle-states = <&cluster0_c4>;

So here and on x1 we use cpu-idle-states instead of putting the idle state
under domain-idle-states in CPU_PDn like on other PSCI OSI mode-supporting
SoCs. IIUC it works out to be the same thing, but maybe we should stick
to the latter for consistency

[...]

> +
> +			gic_its: msi-controller@...40000 {
> +				compatible = "arm,gic-v3-its";
> +				reg = <0x0 0x16040000 0x0 0x20000>;
> +
> +				msi-controller;
> +				#msi-cells = <1>;
> +
> +				status = "disabled";
> +			};

Any reason it's disabled?

LGTM otherwise

Konrad