linux-kernel - RE: [PATCH v7 2/7] Revert "clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate"

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Message-ID:
 <PAXPR04MB8459C6337B096C4326547CD888242@PAXPR04MB8459.eurprd04.prod.outlook.com>
Date: Fri, 15 Nov 2024 10:19:00 +0000
From: Peng Fan <peng.fan@....com>
To: Ying Liu <victor.liu@....com>, "imx@...ts.linux.dev"
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Subject: RE: [PATCH v7 2/7] Revert "clk: imx: clk-imx8mp: Allow media_disp
 pixel clock reconfigure parent rate"

> Subject: [PATCH v7 2/7] Revert "clk: imx: clk-imx8mp: Allow
> media_disp pixel clock reconfigure parent rate"
> 
> This reverts commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155.
> 
> media_disp1_pix clock is the pixel clock of the first i.MX8MP LCDIFv3
> display controller, while media_disp2_pix clock is the pixel clock of the
> second i.MX8MP LCDIFv3 display controller.  The two display
> controllers connect with Samsung MIPI DSI controller and LVDS Display
> Bridge(LDB) respectively.  Since the two display controllers are driven
> by separate DRM driver instances and the two pixel clocks may be
> derived from the same video_pll1_out clock(sys_pll3_out clock could
> be already used to derive audio_axi clock), there is no way to negotiate
> a dynamically changeable video_pll1_out clock rate to satisfy both of
> the two display controllers.  In this case, the only solution to drive
> them with the single video_pll1_out clock is to assign a
> sensible/unchangeable clock rate for video_pll1_out clock.  Thus, there
> is no need to set the CLK_SET_RATE_PARENT flag for
> media_disp{1,2}_pix clocks, drop it then.
> 
> Fixes: ff06ea04e4cf ("clk: imx: clk-imx8mp: Allow media_disp pixel
> clock reconfigure parent rate")
> Signed-off-by: Liu Ying <victor.liu@....com>
> ---

Acked-by: Peng Fan <peng.fan@....com>