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Message-ID: <Zziu8tMZfWpqAur9@lore-rh-laptop>
Date: Sat, 16 Nov 2024 15:40:50 +0100
From: Lorenzo Bianconi <lorenzo@...nel.org>
To: Christian Marangi <ansuelsmth@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
	linux-kernel@...r.kernel.org, upstream@...oha.com,
	stable@...r.kernel.org
Subject: Re: [PATCH] clk: en7523: Fix wrong BUS clock for EN7581

> The Documentation for EN7581 had a typo and still referenced the EN7523
> BUS base source frequency. This was in conflict with a different page in
> the Documentration that state that the BUS runs at 300MHz (600MHz source
> with divisor set to 2) and the actual watchdog that tick at half the BUS
> clock (150MHz). This was verified with the watchdog by timing the
> seconds that the system takes to reboot (due too watchdog) and by
> operating on different values of the BUS divisor.
> 
> The correct values for source of BUS clock are 600MHz and 540MHz.
> 
> This was also confirmed by Airoha.

Acked-by: Lorenzo Bianconi <lorenzo@...nel.org>

> 
> Cc: stable@...r.kernel.org
> Fixes: 66bc47326ce2 ("clk: en7523: Add EN7581 support")
> Signed-off-by: Christian Marangi <ansuelsmth@...il.com>
> ---
>  drivers/clk/clk-en7523.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
> index e52c5460e927..239cb04d9ae3 100644
> --- a/drivers/clk/clk-en7523.c
> +++ b/drivers/clk/clk-en7523.c
> @@ -87,6 +87,7 @@ static const u32 slic_base[] = { 100000000, 3125000 };
>  static const u32 npu_base[] = { 333000000, 400000000, 500000000 };
>  /* EN7581 */
>  static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 };
> +static const u32 bus7581_base[] = { 600000000, 540000000 };
>  static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
>  static const u32 crypto_base[] = { 540000000, 480000000 };
>  
> @@ -222,8 +223,8 @@ static const struct en_clk_desc en7581_base_clks[] = {
>  		.base_reg = REG_BUS_CLK_DIV_SEL,
>  		.base_bits = 1,
>  		.base_shift = 8,
> -		.base_values = bus_base,
> -		.n_base_values = ARRAY_SIZE(bus_base),
> +		.base_values = bus7581_base,
> +		.n_base_values = ARRAY_SIZE(bus7581_base),
>  
>  		.div_bits = 3,
>  		.div_shift = 0,
> -- 
> 2.45.2
> 

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