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Message-ID: <202411161334.rczGLGKY-lkp@intel.com>
Date: Sat, 16 Nov 2024 22:49:28 +0800
From: kernel test robot <lkp@...el.com>
To: Terry Bowman <terry.bowman@....com>, linux-cxl@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
nifan.cxl@...il.com, ming4.li@...el.com, dave@...olabs.net,
jonathan.cameron@...wei.com, dave.jiang@...el.com,
alison.schofield@...el.com, vishal.l.verma@...el.com,
dan.j.williams@...el.com, bhelgaas@...gle.com, mahesh@...ux.ibm.com,
ira.weiny@...el.com, oohall@...il.com, Benjamin.Cheatham@....com,
rrichter@....com, nathan.fontenot@....com,
Smita.KoralahalliChannabasappa@....com, lukas@...ner.de
Cc: oe-kbuild-all@...ts.linux.dev
Subject: Re: [PATCH v3 08/15] cxl/pci: Map CXL PCIe root port and downstream
switch port RAS registers
Hi Terry,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 2d5404caa8c7bb5c4e0435f94b28834ae5456623]
url: https://github.com/intel-lab-lkp/linux/commits/Terry-Bowman/PCI-AER-Introduce-struct-cxl_err_handlers-and-add-to-struct-pci_driver/20241114-060000
base: 2d5404caa8c7bb5c4e0435f94b28834ae5456623
patch link: https://lore.kernel.org/r/20241113215429.3177981-9-terry.bowman%40amd.com
patch subject: [PATCH v3 08/15] cxl/pci: Map CXL PCIe root port and downstream switch port RAS registers
config: i386-randconfig-141-20241116 (https://download.01.org/0day-ci/archive/20241116/202411161334.rczGLGKY-lkp@intel.com/config)
compiler: clang version 19.1.3 (https://github.com/llvm/llvm-project ab51eccf88f5321e7c60591c5546b254b6afab99)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241116/202411161334.rczGLGKY-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411161334.rczGLGKY-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/cxl/core/pci.c:782: warning: Excess function parameter 'host' description in 'cxl_dport_init_ras_reporting'
vim +782 drivers/cxl/core/pci.c
d1a9def33d7043 Terry Bowman 2023-10-18 775
577a67662ff529 Li Ming 2024-08-30 776 /**
577a67662ff529 Li Ming 2024-08-30 777 * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport
577a67662ff529 Li Ming 2024-08-30 778 * @dport: the cxl_dport that needs to be initialized
577a67662ff529 Li Ming 2024-08-30 779 * @host: host device for devm operations
577a67662ff529 Li Ming 2024-08-30 780 */
23f51024741fc0 Terry Bowman 2024-11-13 781 void cxl_dport_init_ras_reporting(struct cxl_dport *dport)
f05fd10d138d8b Robert Richter 2023-10-27 @782 {
23f51024741fc0 Terry Bowman 2024-11-13 783 struct device *dport_dev = dport->dport_dev;
23f51024741fc0 Terry Bowman 2024-11-13 784 struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport_dev);
f05fd10d138d8b Robert Richter 2023-10-27 785
23f51024741fc0 Terry Bowman 2024-11-13 786 if (dport->rch && host_bridge->native_aer) {
23f51024741fc0 Terry Bowman 2024-11-13 787 cxl_dport_map_rch_aer(dport);
23f51024741fc0 Terry Bowman 2024-11-13 788 cxl_disable_rch_root_ints(dport);
23f51024741fc0 Terry Bowman 2024-11-13 789 }
6c5f3aacb2963d Terry Bowman 2023-10-18 790
23f51024741fc0 Terry Bowman 2024-11-13 791 /* dport may have more than 1 downstream EP. Check if already mapped. */
23f51024741fc0 Terry Bowman 2024-11-13 792 if (dport->regs.ras)
c8706cc15a5814 Li Ming 2024-08-30 793 return;
d1a9def33d7043 Terry Bowman 2023-10-18 794
23f51024741fc0 Terry Bowman 2024-11-13 795 dport->reg_map.host = dport_dev;
23f51024741fc0 Terry Bowman 2024-11-13 796 if (cxl_map_component_regs(&dport->reg_map, &dport->regs.component,
23f51024741fc0 Terry Bowman 2024-11-13 797 BIT(CXL_CM_CAP_CAP_ID_RAS))) {
23f51024741fc0 Terry Bowman 2024-11-13 798 dev_err(dport_dev, "Failed to map RAS capability.\n");
23f51024741fc0 Terry Bowman 2024-11-13 799 return;
f05fd10d138d8b Robert Richter 2023-10-27 800 }
c8706cc15a5814 Li Ming 2024-08-30 801 }
577a67662ff529 Li Ming 2024-08-30 802 EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, CXL);
f05fd10d138d8b Robert Richter 2023-10-27 803
--
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