linux-kernel - [PATCH 1/2] mtd: rawnand: qcom: Pass 18 bit offset from QPIC base address to BAM

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Message-ID: <20241119092058.480363-2-quic_mdalam@quicinc.com>
Date: Tue, 19 Nov 2024 14:50:57 +0530
From: Md Sadre Alam <quic_mdalam@...cinc.com>
To: <manivannan.sadhasivam@...aro.org>, <miquel.raynal@...tlin.com>,
        <richard@....at>, <vigneshr@...com>, <linux-mtd@...ts.infradead.org>,
        <linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC: <quic_srichara@...cinc.com>, <quic_nainmeht@...cinc.com>,
        <quic_laksd@...cinc.com>, <quic_varada@...cinc.com>
Subject: [PATCH 1/2] mtd: rawnand: qcom: Pass 18 bit offset from QPIC base address to BAM

Currently we are configuring lower 24 bits of address in descriptor
whereas QPIC design expects 18 bit register offset from QPIC base
address to be configured in cmd descriptors. This is leading to a
different address actually being used in HW, leading to wrong value
read.

Older targets also used same configuration (lower 24 bits) like sdxpinn,
ipq etc. but issue is masked in older targets due to lower 18 bits of QPIC
base address being zero leading to expected address generation.

Sdxpinn     : QPIC_QPIC | 0x01C98000 (Lower 18 bits are non zero)
Sdxnightjar : QPIC_QPIC | 0x07980000 (Lower 18 bits are zero) Same for
older targets.

Signed-off-by: Md Sadre Alam <quic_mdalam@...cinc.com>
---
 drivers/mtd/nand/raw/qcom_nandc.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index b8cff9240b28..34ee8555fb8a 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -207,7 +207,7 @@ nandc_set_reg(chip, reg,			\
 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
 
 /* Returns the NAND register physical address */
-#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
+#define nandc_reg_phys(chip, offset)  ((nandc)->props->offset_from_qpic + (offset))
 
 /* Returns the dma address for reg read buffer */
 #define reg_buf_dma_addr(chip, vaddr) \
@@ -561,6 +561,7 @@ struct qcom_nandc_props {
 	bool is_qpic;
 	bool qpic_v2;
 	bool use_codeword_fixup;
+	u32 offset_from_qpic;
 };
 
 /* Frees the BAM transaction memory */
@@ -3477,6 +3478,7 @@ static const struct qcom_nandc_props ipq806x_nandc_props = {
 	.is_bam = false,
 	.use_codeword_fixup = true,
 	.dev_cmd_reg_start = 0x0,
+	.offset_from_qpic = 0x30000,
 };
 
 static const struct qcom_nandc_props ipq4019_nandc_props = {
@@ -3484,6 +3486,7 @@ static const struct qcom_nandc_props ipq4019_nandc_props = {
 	.is_bam = true,
 	.is_qpic = true,
 	.dev_cmd_reg_start = 0x0,
+	.offset_from_qpic = 0x30000,
 };
 
 static const struct qcom_nandc_props ipq8074_nandc_props = {
@@ -3491,6 +3494,7 @@ static const struct qcom_nandc_props ipq8074_nandc_props = {
 	.is_bam = true,
 	.is_qpic = true,
 	.dev_cmd_reg_start = 0x7000,
+	.offset_from_qpic = 0x30000,
 };
 
 static const struct qcom_nandc_props sdx55_nandc_props = {
@@ -3498,7 +3502,8 @@ static const struct qcom_nandc_props sdx55_nandc_props = {
 	.is_bam = true,
 	.is_qpic = true,
 	.qpic_v2 = true,
-	.dev_cmd_reg_start = 0x7000,
+	.dev_cmd_reg_start = 0x0,
+	.offset_from_qpic = 0x30000,
 };
 
 /*
-- 
2.34.1