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Message-ID: <20241119132916.1057797-2-heiko@sntech.de>
Date: Tue, 19 Nov 2024 14:29:12 +0100
From: Heiko Stuebner <heiko@...ech.de>
To: srinivas.kandagatla@...aro.org
Cc: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
heiko@...ech.de,
detlev.casanova@...labora.com,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org,
sebastian.reichel@...labora.com
Subject: [PATCH 1/5] clk: rockchip: rk3576: define clk_otp_phy_g
The phy clock of the OTP block is also present, but was not defined
so far. Though its clk-id already existed, so just define its location.
Signed-off-by: Heiko Stuebner <heiko@...ech.de>
---
drivers/clk/rockchip/clk-rk3576.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-rk3576.c
index 595e010341f7..029939a98416 100644
--- a/drivers/clk/rockchip/clk-rk3576.c
+++ b/drivers/clk/rockchip/clk-rk3576.c
@@ -541,6 +541,8 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = {
RK3576_CLKGATE_CON(5), 14, GFLAGS),
GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
RK3576_CLKGATE_CON(5), 15, GFLAGS),
+ GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
+ RK3588_CLKGATE_CON(6), 0, GFLAGS),
COMPOSITE(CLK_MIPI_CAMERAOUT_M0, "clk_mipi_cameraout_m0", mux_24m_spll_gpll_cpll_p, 0,
RK3576_CLKSEL_CON(38), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3576_CLKGATE_CON(6), 3, GFLAGS),
--
2.45.2
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