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Message-ID: <2743666a-f592-4ee2-af43-757c6d8ca64c@amd.com>
Date: Tue, 19 Nov 2024 19:06:45 +0530
From: Ravi Bangoria <ravi.bangoria@....com>
To: peterz@...radead.org, mingo@...hat.com, namhyung@...nel.org
Cc: acme@...nel.org, eranian@...gle.com, mark.rutland@....com,
 alexander.shishkin@...ux.intel.com, jolsa@...nel.org, irogers@...gle.com,
 adrian.hunter@...el.com, kan.liang@...ux.intel.com, tglx@...utronix.de,
 bp@...en8.de, dave.hansen@...ux.intel.com, x86@...nel.org, hpa@...or.com,
 linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
 santosh.shukla@....com, ananth.narayan@....com, sandipan.das@....com
Subject: Re: [PATCH] perf/amd/ibs: Add support for OP Load Latency Filtering

On 10-Oct-24 10:38 AM, Ravi Bangoria wrote:
> A new Load Latency Filtering capability is added to IBS Op pmu with
> latest (Zen5) uarch. It's advertised by CPUID_Fn8000001B_EAX bit 12.
> When enabled, IBS hw will raise interrupts only for samples that had
> an IbsDcMissLat value greater than N cycles, where N is a programmable
> value defined as multiples of 128 (i.e., 128, 256, 512 etc.) from
> 128-2048 cycles. L3MissOnly is a mandatory dependency for LdLat, and
> like L3MissOnly, Hardware internally drops the sample and restarts if
> the sample does not meet the filtering condition.
> 
> Add support for LdLat filtering in IBS Op pmu. Since hardware supports
> threshold in multiple of 128, add a software filter on top to support
> latency threshold with the granularity of 1 cycle between [128-2048].
> 
> Example usage:
>   # perf record -a -e ibs_op/l3missonly=1,ldlat=128/ -- sleep 5
> 
> Signed-off-by: Ravi Bangoria <ravi.bangoria@....com>
> ---
> 
> Note: IBS sample period cleanup patches are pre-req for this.
>       https://lore.kernel.org/r/20241007034810.754-1-ravi.bangoria@amd.com

Peter/Ingo, gentle reminder.

Thanks,
Ravi

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