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Message-Id: <20241119135504.1463839-1-kan.liang@linux.intel.com>
Date: Tue, 19 Nov 2024 05:55:00 -0800
From: kan.liang@...ux.intel.com
To: peterz@...radead.org,
mingo@...hat.com,
linux-kernel@...r.kernel.org
Cc: acme@...nel.org,
namhyung@...nel.org,
irogers@...gle.com,
eranian@...gle.com,
ak@...ux.intel.com,
dapeng1.mi@...ux.intel.com,
Kan Liang <kan.liang@...ux.intel.com>
Subject: [PATCH V2 0/4] PEBS DS bug fix and optimization
From: Kan Liang <kan.liang@...ux.intel.com>
Changes since V1:
- Fix a PEBS DS bug which also impacts the existing implementation (new)
- Factor out generic functions for PEBS records processing (Peter)
- Update the description to explain the reason of moving
intel_pmu_save_and_restart() related codes to the end and droping
the return.
The V1 can be found at
https://lore.kernel.org/lkml/20241113151427.677169-1-kan.liang@linux.intel.com/
Kan Liang (4):
perf/x86/intel/ds: Unconditionally drain PEBS DS when changing
PEBS_DATA_CFG
perf/x86/intel/ds: Clarify adaptive PEBS processing
perf/x86/intel/ds: Factor out functions for PEBS records processing
perf/x86/intel/ds: Simplify the PEBS records processing for adaptive
PEBS
arch/x86/events/intel/ds.c | 191 ++++++++++++++++++------------
arch/x86/include/asm/perf_event.h | 16 ++-
2 files changed, 128 insertions(+), 79 deletions(-)
--
2.38.1
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