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Message-Id: <20241120-a5-clk-v2-2-1208621e961d@amlogic.com>
Date: Wed, 20 Nov 2024 15:01:14 +0800
From: Xianwei Zhao via B4 Relay <devnull+xianwei.zhao.amlogic.com@...nel.org>
To: Neil Armstrong <neil.armstrong@...aro.org>,
Jerome Brunet <jbrunet@...libre.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Chuan Liu <chuan.liu@...ogic.com>,
Kevin Hilman <khilman@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc: linux-amlogic@...ts.infradead.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Xianwei Zhao <xianwei.zhao@...ogic.com>
Subject: [PATCH v2 2/5] dt-bindings: clock: add Amlogic A5 SCMI clock
controller support
From: Chuan Liu <chuan.liu@...ogic.com>
Add the SCMI clock controller dt-bindings for Amlogic A5 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@...ogic.com>
Reviewed-by: Rob Herring (Arm) <robh@...nel.org>
Signed-off-by: Xianwei Zhao <xianwei.zhao@...ogic.com>
---
include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 ++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h
new file mode 100644
index 000000000000..1bf027d0110a
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@...ogic.com>
+ */
+
+#ifndef __AMLOGIC_A5_SCMI_CLKC_H
+#define __AMLOGIC_A5_SCMI_CLKC_H
+
+#define CLKID_OSC 0
+#define CLKID_SYS_CLK 1
+#define CLKID_AXI_CLK 2
+#define CLKID_CPU_CLK 3
+#define CLKID_DSU_CLK 4
+#define CLKID_GP1_PLL 5
+#define CLKID_FIXED_PLL_DCO 6
+#define CLKID_FIXED_PLL 7
+#define CLKID_ACLKM 8
+#define CLKID_SYS_PLL_DIV16 9
+#define CLKID_CPU_CLK_DIV16 10
+#define CLKID_FCLK_50M_PREDIV 11
+#define CLKID_FCLK_50M_DIV 12
+#define CLKID_FCLK_50M 13
+#define CLKID_FCLK_DIV2_DIV 14
+#define CLKID_FCLK_DIV2 15
+#define CLKID_FCLK_DIV2P5_DIV 16
+#define CLKID_FCLK_DIV2P5 17
+#define CLKID_FCLK_DIV3_DIV 18
+#define CLKID_FCLK_DIV3 19
+#define CLKID_FCLK_DIV4_DIV 20
+#define CLKID_FCLK_DIV4 21
+#define CLKID_FCLK_DIV5_DIV 22
+#define CLKID_FCLK_DIV5 23
+#define CLKID_FCLK_DIV7_DIV 24
+#define CLKID_FCLK_DIV7 25
+#define CLKID_SYS_MMC_PCLK 26
+#define CLKID_SYS_CPU_CTRL 27
+#define CLKID_SYS_IRQ_CTRL 28
+#define CLKID_SYS_GIC 29
+#define CLKID_SYS_BIG_NIC 30
+#define CLKID_AXI_SYS_NIC 31
+#define CLKID_AXI_CPU_DMC 32
+
+#endif /* __AMLOGIC_A5_SCMI_CLKC_H */
--
2.37.1
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