linux-kernel - Re: [PATCH V5 1/4] dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P

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Message-ID: <10e4fd4e-559d-4164-ab94-d5f0a60ffc22@quicinc.com>
Date: Thu, 21 Nov 2024 23:13:29 +0530
From: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
To: Krzysztof Kozlowski <krzk@...nel.org>, Georgi Djakov <djakov@...nel.org>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>
CC: Odelu Kukatla <quic_okukatla@...cinc.com>,
        Mike Tipton
	<quic_mdtipton@...cinc.com>,
        Sibi Sankar <quic_sibis@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
        <linux-pm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V5 1/4] dt-bindings: interconnect: Add EPSS L3 compatible
 for SA8775P



On 11/21/2024 5:23 PM, Krzysztof Kozlowski wrote:
> On 21/11/2024 12:30, Raviteja Laggyshetty wrote:
>> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on
>> SA8775P SoCs.
> 
> This we see from the diff. Explain the hardware, why adding epps-l3-perf.
> 
The EPSS instance in SA8775P uses PERF_STATE register instead of REG_L3_VOTE to scale L3 clocks.Along with SoC specific compatible, add new generic compatible "qcom,epss-l3-perf" for PERF_STATE register based L3 scaling.

>>
>> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
>> ---
>>  .../devicetree/bindings/interconnect/qcom,osm-l3.yaml         | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>> index 21dae0b92819..042ca44c32ec 100644
>> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>> @@ -34,6 +34,10 @@ properties:
>>                - qcom,sm8250-epss-l3
>>                - qcom,sm8350-epss-l3
>>            - const: qcom,epss-l3
>> +      - items:
>> +          - enum:
>> +              - qcom,sa8775p-epss-l3
>> +          - const: qcom,epss-l3-perf
> 
> I don't understand this change in context of driver. These are the same.
> Isn't this compatible with sm8250?
> 

The intention for adding "qcom,epss-l3-perf" generic compatible is to use it for the chipsets which use perf state register for l3 scaling.
Using generic compatible avoids the need for adding chipset specific compatible in match table.
But received comment from konrad to add both SoC-specific and generic compatibles.
Dmitry has suggested to update generic comaptibles for sc7280 and sm8250 SoCs, which makes use of perf state registers. 
It will be done as separate patch series.


> Sorry, this is all (binding plus driver) quite confusing.
> 
> Best regards,
> Krzysztof