linux-kernel - [PATCH 1/3] dt-bindings: memory-controllers: Add support for Versal NET EDAC

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Message-ID: <20241122100625.24571-2-shubhrajyoti.datta@amd.com>
Date: Fri, 22 Nov 2024 15:36:23 +0530
From: Shubhrajyoti Datta <shubhrajyoti.datta@....com>
To: <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
	<linux-edac@...r.kernel.org>
CC: <git@....com>, <krzk@...nel.or>, <robh@...nel.org>, <conor+dt@...nel.org>,
	<bp@...en8.de>, <tony.luck@...el.com>, <james.morse@....com>,
	<mchehab@...nel.org>, <rric@...nel.org>
Subject: [PATCH 1/3] dt-bindings: memory-controllers: Add support for Versal NET EDAC

Add device tree bindings for AMD Versal NET EDAC for DDR controller.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@....com>
---

 .../amd,versalnet-edac.yaml                   | 56 +++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/amd,versalnet-edac.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/amd,versalnet-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/amd,versalnet-edac.yaml
new file mode 100644
index 000000000000..22a4669c46b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/amd,versalnet-edac.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/amd,versalnet-edac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AMD Versal NET EDAC
+
+maintainers:
+  - Shubhrajyoti Datta <shubhrajyoti.datta@....com>
+
+description:
+  The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
+  4X memory interfaces. Versal NET DDR memory controller has an optional ECC support
+  which correct single bit ECC errors and detect double bit ECC errors.
+  It also has support for reporting other errors like MMCM (Mixed-Mode Clock
+  Manager) errors and General software errors.
+
+properties:
+  compatible:
+    const: amd,versalnet-edac
+
+  amd,dwidth:
+    description:
+      DDR memory controller device width.
+    enum: [16, 32]
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  amd,num-chans:
+    description:
+      Number of channels.
+    enum: [1, 2]
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  amd,num-rank:
+    description:
+      Number of rank.
+    enum: [1, 2, 4]
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+  - compatible
+  - amd,dwidth
+  - amd,num-chans
+  - amd,num-rank
+
+additionalProperties: false
+
+examples:
+  - |
+    memory-controller {
+       compatible = "amd,versalnet-edac";
+       amd,dwidth = <32>;
+       amd,num-chans = <2>;
+       amd,num-rank = <1>;
+     };
-- 
2.17.1