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Message-Id: <20241122020305.1584577-7-quic_ziyuzhan@quicinc.com>
Date: Fri, 22 Nov 2024 10:03:05 +0800
From: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
To: vkoul@...nel.org, kishon@...nel.org, robh+dt@...nel.org,
        manivannan.sadhasivam@...aro.org, bhelgaas@...gle.com, kw@...ux.com,
        lpieralisi@...nel.org, quic_qianyu@...cinc.com, conor+dt@...nel.org,
        neil.armstrong@...aro.org, andersson@...nel.org,
        konradybcio@...nel.org
Cc: quic_tsoni@...cinc.com, quic_shashim@...cinc.com,
        quic_kaushalk@...cinc.com, quic_tdas@...cinc.com,
        quic_tingweiz@...cinc.com, quic_aiquny@...cinc.com, kernel@...cinc.com,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
        Krishna chaitanya chundru <quic_krichai@...cinc.com>,
        Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Subject: [PATCH v2 6/6] arm64: dts: qcom: qcs615: enable pcie for qcs615 platform dts

From: Krishna chaitanya chundru <quic_krichai@...cinc.com>

Add platform configurations in devicetree for PCIe, board related
gpios, PMIC regulators, etc.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615-ride.dts | 42 ++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index ee6cab3924a6..18f131ae9e07 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -202,6 +202,23 @@ &gcc {
 		 <&sleep_clk>;
 };
 
+&pcie {
+	perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
+
+	pinctrl-0 = <&pcie_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie_phy {
+	vdda-phy-supply = <&vreg_l5a>;
+	vdda-pll-supply = <&vreg_l12a>;
+
+	status = "okay";
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
@@ -210,6 +227,31 @@ &rpmhcc {
 	clocks = <&xo_board_clk>;
 };
 
+&tlmm {
+	pcie_default_state: pcie-default-state {
+		clkreq-pins {
+			pins = "gpio90";
+			function = "pcie_clk_req";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-pins {
+			pins = "gpio101";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+
+		wake-pins {
+			pins = "gpio100";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+};
+
 &uart0 {
 	status = "okay";
 };
-- 
2.34.1


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