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Message-ID: <w3rqdjygedgwsacn4ybajvv3fwuhhaaazo5x7zqcip7xdtf4lo@shwsl5acgqzk>
Date: Sat, 23 Nov 2024 06:24:48 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Bibek Kumar Patro <quic_bibekkum@...cinc.com>
Cc: robdclark@...il.com, will@...nel.org, robin.murphy@....com,
joro@...tes.org, jgg@...pe.ca, jsnitsel@...hat.com, robh@...nel.org,
krzysztof.kozlowski@...aro.org, quic_c_gdjako@...cinc.com, iommu@...ts.linux.dev,
linux-arm-msm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH RESEND v17 4/5] iommu/arm-smmu: introduction of ACTLR for
custom prefetcher settings
On Thu, Nov 14, 2024 at 09:37:20PM +0530, Bibek Kumar Patro wrote:
> Currently in Qualcomm SoCs the default prefetch is set to 1 which allows
> the TLB to fetch just the next page table. MMU-500 features ACTLR
> register which is implementation defined and is used for Qualcomm SoCs
> to have a custom prefetch setting enabling TLB to prefetch the next set
> of page tables accordingly allowing for faster translations.
>
> ACTLR value is unique for each SMR (Stream matching register) and stored
> in a pre-populated table. This value is set to the register during
> context bank initialisation.
>
> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@...cinc.com>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 33 ++++++++++++++++++++++
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 1 +
> 2 files changed, 34 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
--
With best wishes
Dmitry
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