[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <20241125163103.4166207-1-ciprianmarian.costea@oss.nxp.com>
Date: Mon, 25 Nov 2024 18:30:59 +0200
From: Ciprian Costea <ciprianmarian.costea@....nxp.com>
To: Marc Kleine-Budde <mkl@...gutronix.de>,
Vincent Mailhol <mailhol.vincent@...adoo.fr>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-can@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
NXP S32 Linux <s32@....com>,
imx@...ts.linux.dev,
Christophe Lizzi <clizzi@...hat.com>,
Alberto Ruiz <aruizrui@...hat.com>,
Enric Balletbo <eballetb@...hat.com>,
Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
Subject: [PATCH v2 0/3] add FlexCAN support for S32G2/S32G3 SoCs
From: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
S32G2 and S32G3 SoCs share the FlexCAN module with i.MX SoCs, with some
hardware integration particularities.
Main difference covered by this patchset relates to interrupt management.
On S32G2/S32G3 SoC, there are separate interrupts for state change, bus
errors, MBs 0-7 and MBs 8-127 respectively.
Changes in V2:
- Separated 'FLEXCAN_QUIRK_NR_IRQ_3' quirk addition from S32G SoC Flexcan
support.
- Provided more information in dt-bindings documentation with respect to
FlexCAN module integration on S32G SoCs.
- Fixed and irq resource freeing management issue.
Ciprian Marian Costea (3):
dt-bindings: can: fsl,flexcan: add S32G2/S32G3 SoC support
can: flexcan: Add quirk to handle separate interrupt lines for
mailboxes
can: flexcan: add NXP S32G2/S32G3 SoC support
.../bindings/net/can/fsl,flexcan.yaml | 46 +++++++++++++++++--
drivers/net/can/flexcan/flexcan-core.c | 35 +++++++++++++-
drivers/net/can/flexcan/flexcan.h | 5 ++
3 files changed, 81 insertions(+), 5 deletions(-)
--
2.45.2
Powered by blists - more mailing lists