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Message-ID: <a46b4151-fa44-4ec9-80f1-f3151749c529@linaro.org>
Date: Mon, 25 Nov 2024 09:14:59 +0100
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Akhil P Oommen <quic_akhilpo@...cinc.com>
Cc: Viresh Kumar <vireshk@...nel.org>, Nishanth Menon <nm@...com>,
Stephen Boyd <sboyd@...nel.org>, "Rafael J. Wysocki" <rafael@...nel.org>,
Rob Clark <robdclark@...il.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konradybcio@...nel.org>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Connor Abbott <cwabbott0@...il.com>,
linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v2 02/11] drm/msm: adreno: rename quirks that are features
On 23/11/2024 20:25, Akhil P Oommen wrote:
> On Tue, Nov 19, 2024 at 06:56:37PM +0100, Neil Armstrong wrote:
>> Half of the current "Quirks" are in fact features, so rename
>> the defines with FEAT instead of QUIRK.
>>
>> They will be moved in a separate bitfield in a second time.
>>
>> No functional changes.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 62 +++++++++++++++---------------
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +-
>> drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +-
>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++--
>> 4 files changed, 38 insertions(+), 37 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..825c820def315968d508973c8ae40c7c7b646569 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -743,7 +743,7 @@ static const struct adreno_info a6xx_gpus[] = {
>> },
>> .gmem = SZ_512K,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT,
>> .init = a6xx_gpu_init,
>> .zapfw = "a615_zap.mbn",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -769,7 +769,7 @@ static const struct adreno_info a6xx_gpus[] = {
>> },
>> .gmem = SZ_512K,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT,
>> .init = a6xx_gpu_init,
>> .a6xx = &(const struct a6xx_info) {
>> .protect = &a630_protect,
>> @@ -839,7 +839,7 @@ static const struct adreno_info a6xx_gpus[] = {
>> },
>> .gmem = SZ_512K,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT,
>> .init = a6xx_gpu_init,
>> .zapfw = "a615_zap.mdt",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -864,8 +864,8 @@ static const struct adreno_info a6xx_gpus[] = {
>> },
>> .gmem = SZ_512K,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> - ADRENO_QUIRK_HAS_HW_APRIV,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT |
>> + ADRENO_FEAT_HAS_HW_APRIV,
>> .init = a6xx_gpu_init,
>> .zapfw = "a620_zap.mbn",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -892,7 +892,7 @@ static const struct adreno_info a6xx_gpus[] = {
>> },
>> .gmem = SZ_1M,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT,
>> .init = a6xx_gpu_init,
>> .zapfw = "a630_zap.mdt",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -911,7 +911,7 @@ static const struct adreno_info a6xx_gpus[] = {
>> },
>> .gmem = SZ_1M,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT,
>> .init = a6xx_gpu_init,
>> .zapfw = "a640_zap.mdt",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -934,8 +934,8 @@ static const struct adreno_info a6xx_gpus[] = {
>> },
>> .gmem = SZ_1M + SZ_128K,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> - ADRENO_QUIRK_HAS_HW_APRIV,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT |
>> + ADRENO_FEAT_HAS_HW_APRIV,
>> .init = a6xx_gpu_init,
>> .zapfw = "a650_zap.mdt",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -961,8 +961,8 @@ static const struct adreno_info a6xx_gpus[] = {
>> },
>> .gmem = SZ_1M + SZ_512K,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> - ADRENO_QUIRK_HAS_HW_APRIV,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT |
>> + ADRENO_FEAT_HAS_HW_APRIV,
>> .init = a6xx_gpu_init,
>> .zapfw = "a660_zap.mdt",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -981,8 +981,8 @@ static const struct adreno_info a6xx_gpus[] = {
>> },
>> .gmem = SZ_1M + SZ_512K,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> - ADRENO_QUIRK_HAS_HW_APRIV,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT |
>> + ADRENO_FEAT_HAS_HW_APRIV,
>> .init = a6xx_gpu_init,
>> .a6xx = &(const struct a6xx_info) {
>> .hwcg = a690_hwcg,
>> @@ -1000,8 +1000,8 @@ static const struct adreno_info a6xx_gpus[] = {
>> },
>> .gmem = SZ_512K,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> - ADRENO_QUIRK_HAS_HW_APRIV,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT |
>> + ADRENO_FEAT_HAS_HW_APRIV,
>> .init = a6xx_gpu_init,
>> .zapfw = "a660_zap.mbn",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -1028,7 +1028,7 @@ static const struct adreno_info a6xx_gpus[] = {
>> },
>> .gmem = SZ_2M,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT,
>> .init = a6xx_gpu_init,
>> .zapfw = "a640_zap.mdt",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -1046,8 +1046,8 @@ static const struct adreno_info a6xx_gpus[] = {
>> },
>> .gmem = SZ_4M,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> - ADRENO_QUIRK_HAS_HW_APRIV,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT |
>> + ADRENO_FEAT_HAS_HW_APRIV,
>> .init = a6xx_gpu_init,
>> .zapfw = "a690_zap.mdt",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -1331,7 +1331,7 @@ static const struct adreno_info a7xx_gpus[] = {
>> },
>> .gmem = SZ_128K,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
>> + .quirks = ADRENO_FEAT_HAS_HW_APRIV,
>> .init = a6xx_gpu_init,
>> .zapfw = "a702_zap.mbn",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -1355,9 +1355,9 @@ static const struct adreno_info a7xx_gpus[] = {
>> },
>> .gmem = SZ_2M,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> - ADRENO_QUIRK_HAS_HW_APRIV |
>> - ADRENO_QUIRK_PREEMPTION,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT |
>> + ADRENO_FEAT_HAS_HW_APRIV |
>> + ADRENO_FEAT_PREEMPTION,
>> .init = a6xx_gpu_init,
>> .zapfw = "a730_zap.mdt",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -1377,9 +1377,9 @@ static const struct adreno_info a7xx_gpus[] = {
>> },
>> .gmem = 3 * SZ_1M,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> - ADRENO_QUIRK_HAS_HW_APRIV |
>> - ADRENO_QUIRK_PREEMPTION,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT |
>> + ADRENO_FEAT_HAS_HW_APRIV |
>> + ADRENO_FEAT_PREEMPTION,
>> .init = a6xx_gpu_init,
>> .zapfw = "a740_zap.mdt",
>> .a6xx = &(const struct a6xx_info) {
>> @@ -1400,9 +1400,9 @@ static const struct adreno_info a7xx_gpus[] = {
>> },
>> .gmem = 3 * SZ_1M,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> - ADRENO_QUIRK_HAS_HW_APRIV |
>> - ADRENO_QUIRK_PREEMPTION,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT |
>> + ADRENO_FEAT_HAS_HW_APRIV |
>> + ADRENO_FEAT_PREEMPTION,
>> .init = a6xx_gpu_init,
>> .a6xx = &(const struct a6xx_info) {
>> .hwcg = a740_hwcg,
>> @@ -1422,9 +1422,9 @@ static const struct adreno_info a7xx_gpus[] = {
>> },
>> .gmem = 3 * SZ_1M,
>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> - ADRENO_QUIRK_HAS_HW_APRIV |
>> - ADRENO_QUIRK_PREEMPTION,
>> + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT |
>> + ADRENO_FEAT_HAS_HW_APRIV |
>> + ADRENO_FEAT_PREEMPTION,
>> .init = a6xx_gpu_init,
>> .zapfw = "gen70900_zap.mbn",
>> .a6xx = &(const struct a6xx_info) {
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index 019610341df1506c89f44e86b8d1deeb27d61857..2ebd3fac212576a1507e0b6afe2560cd0408dd89 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -2478,7 +2478,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
>> adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper");
>>
>> adreno_gpu->base.hw_apriv =
>> - !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
>> + !!(config->info->quirks & ADRENO_FEAT_HAS_HW_APRIV);
>>
>> /* gpu->info only gets assigned in adreno_gpu_init() */
>> is_a7xx = config->info->family == ADRENO_7XX_GEN1 ||
>> @@ -2495,7 +2495,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
>> }
>>
>> if ((enable_preemption == 1) || (enable_preemption == -1 &&
>> - (config->info->quirks & ADRENO_QUIRK_PREEMPTION)))
>> + (config->info->quirks & ADRENO_FEAT_PREEMPTION)))
>> ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4);
>> else if (is_a7xx)
>> ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1);
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
>> index 9ffe91920fbfb4841b28aabec9fbde94539fdd83..09d4569f77528c2a20cabc814668c4c930dd07f1 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
>> @@ -207,7 +207,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
>>
>> priv->is_a2xx = info->family < ADRENO_3XX;
>> priv->has_cached_coherent =
>> - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
>> + !!(info->quirks & ADRENO_FEAT_HAS_CACHED_COHERENT);
>>
>> gpu = info->init(drm);
>> if (IS_ERR(gpu)) {
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> index e71f420f8b3a8e6cfc52dd1c4d5a63ef3704a07f..8782c25e8a393ec7d9dc23ad450908d039bd08c5 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> @@ -54,9 +54,10 @@ enum adreno_family {
>> #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
>> #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
>> #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
>> -#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
>> -#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
>> -#define ADRENO_QUIRK_PREEMPTION BIT(5)
>> +
>
> IMO, we should not keep features separate. In future, we should just append the next
> quirk/feature at the bottom without disturbing the existing bit
> mappings. Just to ensure we don't accidentally duplicate a bit number.
>
> I agree on using 'ADRENO_FEAT' to distinguish features.
Ack, this is the conclusion on patch 3, I'll drop the next one and not
separate the flags.
Neil
>
> -Akhil
>
>> +#define ADRENO_FEAT_HAS_HW_APRIV BIT(3)
>> +#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(4)
>> +#define ADRENO_FEAT_PREEMPTION BIT(5)
>>
>> /* Helper for formating the chip_id in the way that userspace tools like
>> * crashdec expect.
>>
>> --
>> 2.34.1
>>
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