Message-ID: <3f26c0b6-e010-4dfc-b5c3-7659f341dbe1@intel.com>
Date: Tue, 26 Nov 2024 11:01:20 -0800
From: Reinette Chatre <reinette.chatre@...el.com>
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Subject: Re: [PATCH v9 08/26] x86/resctrl: Introduce the interface to display
 monitor mode

Hi Babu,

On 11/26/24 9:09 AM, Moger, Babu wrote:
> On 11/25/2024 12:17 PM, Reinette Chatre wrote:
>> On 11/22/24 4:02 PM, Moger, Babu wrote:
>>> On 11/22/2024 3:37 PM, Reinette Chatre wrote:
>>>> On 11/22/24 10:25 AM, Moger, Babu wrote:
>>>>> On 11/18/2024 4:07 PM, Reinette Chatre wrote:
>>>>>> On 11/18/24 11:04 AM, Moger, Babu wrote:
>>>>>>> On 11/15/24 18:00, Reinette Chatre wrote:
>>>>>>>> On 10/29/24 4:21 PM, Babu Moger wrote:

>>>>>>>> I'm concerned that users with Intel platforms may want to use the "mbm_cntr_assign" mode
>>>>>>>> to make the event data "more predictable" and then be concerned when the mode does
>>>>>>>> not exist.
>>>>>>>>
>>>>>>>> As an alternative, is it possible to know the number of hardware counters on AMD systems
>>>>>>>> without ABMC? I wonder if we could perhaps always expose num_mbm_cntrs as a way for
>>>>>>>> users to know if their platform may be impacted by this type of "unpredictability" (by comparing
>>>>>>>> num_mbm_cntrs to num_rmids).
>>>>>>>
>>>>>>> There is some round about(or hacky) way to find that out number of RMIDs
>>>>>>> that can be active.
>>>>>>
>>>>>> Does this give consistent and accurate data? Is this something that can be added to resctrl?
>>>>>> (Reading your other message [1] it does not sound as though it can produce an accurate
>>>>>> number on boot.)
>>>>>> If not then it will be up to the documentation to be accurate.
>>>>>>
>>>>>>
>>>>>>>>> +
>>>>>>>>> +    AMD Platforms with ABMC (Assignable Bandwidth Monitoring Counters) feature
>>>>>>>>> +    enable this mode by default so that counters remain assigned even when the
>>>>>>>>> +    corresponding RMID is not in use by any processor.
>>>>>>>>> +
>>>>>>>>> +    "default":
>>>>>>>>> +
>>>>>>>>> +    In default mode resctrl assumes there is a hardware counter for each
>>>>>>>>> +    event within every CTRL_MON and MON group. Reading mbm_total_bytes or
>>>>>>>>> +    mbm_local_bytes may report 'Unavailable' if there is no counter associated
>>>>>>>>> +    with that event.
>>>>>>>>
>>>>>>>> If I understand correctly, on AMD platforms without ABMC the events only report
>>>>>>>> "Unavailable" if there is no counter assigned at the time of the query. If a counter
>>>>>>>> is unassigned and then reassigned then the event count will reset and the user
>>>>>>>> will get some data back but it may thus be unpredictable (to match earlier language).
>>>>>>>> Is this correct? Any AMD platform in "default" mode may thus be vulnerable to
>>>>>>>> "unpredictable" event counts (not just "Unavailable") ... this gets complicated
>>>>>>>
>>>>>>> Yes. All the AMD systems without ABMC are affected by this problem.
>>>>>>>
>>>>>>>> because users should be steered to avoid "default" mode if mbm_assign_mode is
>>>>>>>> available, while not be made concerned to use "default" mode on Intel where
>>>>>>>> mbm_assign_mode is not available.
>>>>>>>
>>>>>>> Can we add text to clarify this?
>>>>>>
>>>>>> Please do.
>>>>>
>>>>> I think we need to add text about AMD systems. How about this?
>>>>>
>>>>> "default":
>>>>> In default mode resctrl assumes there is a hardware counter for each
>>>>> event within every CTRL_MON and MON group. On AMD systems with 16 more monitoring groups, reading mbm_total_bytes or mbm_local_bytes may report 'Unavailable' if there is no counter associated with that event. It is therefore recommended to use the 'mbm_cntr_assign' mode, if supported."
>>>>
>>>>
>>>> What is meant with "On AMD systems with 16 more monitoring groups"? First, the language is
>>>> not clear, second, you mentioned earlier that there is just a "hacky" way to determine number
>>>> of RMIDs that can be active but here "16" is made official in the documentation?
>>>>
>>>
>>> The lowest active RMID is 16. I could not get it using the hacky way.
>>> I have verified testing on all the previous generation of AMD systems by creating the monitoring groups until it reports "Unavailable".
>>> In recent systems it is 32.  We can drop the exact number to be generic.
>>>
>>>
>>> There is no clear documentation on that.  Here is what the doc says.
>>>
>>> A given implementation may have insufficient hardware to simultaneously track the bandwidth for all RMID values which the hardware supports. If an attempt is made to read a Bandwidth Count for an RMID that has been impacted by these hardware limitations, the “U” bit of the
>>> QM_CTR will be set when the counter is read. Subsequent QM_CTR reads for that RMID and Event may return a value with the "U" bit clear. Potential causes of the “U” bit being set include (but are not limited to)
>>>
>>> • RMID is not currently tracked by the hardware.
>>> • RMID was not tracked by the hardware at some time since it was last read.
>>> • RMID has not been read since it started being tracked by the hardware.
>>>
>>> All RMIDs which are currently in use by one or more processors in the QOS domain will be tracked. The hardware will always begin tracking a new RMID value when it gets written to the PQR_ASSOC register of any of the processors in the QOS domain and it is not already being tracked. When the hardware begins tracking an RMID that it was not previously tracking, it will clear the QM_CTR for all events in the new RMID
>>>
>>> - Babu Moger
>>>
>>
>> I think I am starting to understand what is meant with the "count the traffic in an
>> unpredictable way". From what I understand the hardware uses the "U" bit to indicate
>> that an RMID was not tracked for a while, but it only sets this bit on the
>> first read. After that the "U" bit may be cleared if a counter can be assigned to an RMID
>> afterwards.
>> If it was only user space that reads the data then it should be clear to the user when the
>> hardware limitation is encountered and thus hardware behavior can be "predictable", but since
>> the overflow handler runs once per second it may indeed be the overflow handler that
>> encounters the "U" bit and that bit is not currently handled. This could leave user space
>> with impression that events are always returning data but that data may indeed be wrong.
>>
>> In another thread [1] Tony confirmed that "U" bit is not returned by Intel systems so
>> this issue only impacts AMD. As I understand the other scenarios in which AMD systems
>> can return "U" (the first read after assigning an RMID and the first read after changing
>> the memory config) are all scenarios that can be controlled by resctrl.
>>
>> I do not see why unpredictable data should be addressed with documentation. Could this not be
>> fixed instead? Essentially stating "AMD systems without ABMC count the traffic in an unpredictable
>> way" seems like a poor user experience.
>> What if instead resctrl handles the "U" bit better? For example, when the overflow
>> handler encounters the "U" bit the RMID can be permanently marked as "Unavailable"? Would
>> that not be better than the counter behaving unpredictably with users never knowing if they
>> can trust the event counters?
> 
> Actually, I was looking at handling "Unavailable" in little bit better way. Right now, I see it reports "Unavailable" first then it goes into overflow and stays in overflow forever.

Could you please elaborate what you mean with "stays in overflow forever"?

> 
> Also setting the RMID Unavailable permanently is not a good option. We should have a way to reset it. At some later point the RMID can become active and report the correct numbers.

I assume that when an RMID becomes active cannot be the trigger to reset it since user space cannot
then be aware that a counter was not available for a while.

> I was thinking of introducing a new arch state(in arch_mbm_state) to handle this case. Need to investigate more on this. What do you think?
> 

Some new state is surely needed to reflect that the RMID's data may be wrong. It is not clear to
me how you envision the reset of the state. If it is driven from user space then I expect that
resctrl needs to be taught something about this and it cannot just be buried in arch code.

Reinette

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