linux-kernel - Re: [PATCH v2 3/7] riscv: convert bottom half of exception handling to C

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Message-ID: <Z0URd1oF6FnJGXa8@debug.ba.rivosinc.com>
Date: Mon, 25 Nov 2024 16:08:23 -0800
From: Deepak Gupta <debug@...osinc.com>
To: Jisheng Zhang <jszhang@...nel.org>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Charlie Jenkins <charlie@...osinc.com>,
	Clement Leger <cleger@...osinc.com>,
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 3/7] riscv: convert bottom half of exception handling
 to C

On Sun, Jul 21, 2024 at 01:12:28AM +0800, Jisheng Zhang wrote:
>For readability, maintainability and future scalability, convert the
>bottom half of the exception handling to C.
>
>Mostly the assembly code is converted to C in a relatively
>straightforward manner.
>
>However, there are two modifications I need to mention:
>
>1. the cause I.E the CSR_CAUSE value is passed to do_traps() via. 2nd
>param, do_traps() doesn't get it from pt_regs because this way an extra
>memory load is needed, the exception handling sits in hot code path,
>every instruction matters.
>
>2.To cope with SIFIVE_CIP_453 errata, it looks like we don't need
>alternative mechanism any more after the asm->c conversion. Just
>replace the excp_vect_table two entries.
>
>Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
>---
> arch/riscv/errata/sifive/errata.c       | 25 ++++++++---
> arch/riscv/include/asm/asm-prototypes.h |  1 +
> arch/riscv/include/asm/errata_list.h    |  5 +--
> arch/riscv/kernel/entry.S               | 57 +------------------------
> arch/riscv/kernel/traps.c               | 37 ++++++++++++++++
> 5 files changed, 61 insertions(+), 64 deletions(-)
>
Sorry for noticing it so late. And thanks to Bjorn for pointing it out.
lgtm.

Reviewed-by: Deepak Gupta <debug@...osinc.com>