linux-kernel - Re: [PATCH v3 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2

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Message-ID: <03b6f863-ccdd-4e07-9574-ee9dd7c20ab5@kernel.org>
Date: Tue, 26 Nov 2024 10:26:57 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
 Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Yuanjie Yang <quic_yuanjiey@...cinc.com>, ulf.hansson@...aro.org,
 robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
 bhupesh.sharma@...aro.org, andersson@...nel.org, konradybcio@...nel.org,
 linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
 quic_tingweiz@...cinc.com
Subject: Re: [PATCH v3 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2

On 26/11/2024 01:07, Dmitry Baryshkov wrote:
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> index 590beb37f441..37c6ab217c96 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> @@ -399,6 +399,65 @@ qfprom: efuse@...000 {
>>>  			#size-cells = <1>;
>>>  		};
>>>  
>>> +		sdhc_1: mmc@...000 {
>>> +			compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
>>> +			reg = <0x0 0x007c4000 0x0 0x1000>,
>>> +			      <0x0 0x007c5000 0x0 0x1000>;
>>> +			reg-names = "hc",
>>> +				    "cqhci";
>>
>> There's an "ice" region at 0x007c8000
> 
> Shouldn't ice now be handled by a separate device?
It should and UFS bindings expect that. However I am not sure if MMC was
improved to support external ICE device.  Also for example on SM8550 the
ICE has entirely different (further) address space, so it also suggests
it is separate device. Here address space looks almost continuous.


Best regards,
Krzysztof