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Message-ID: <fde04f06-df39-41a8-8f74-036e315e9a8b@lunn.ch>
Date: Tue, 26 Nov 2024 14:48:19 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Frank Sae <Frank.Sae@...or-comm.com>
Cc: davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
pabeni@...hat.com, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org, xiaogang.fan@...or-comm.com,
fei.zhang@...or-comm.com, hua.sun@...or-comm.com
Subject: Re: [PATCH net-next v2 05/21] motorcomm:yt6801: Implement the
fxgmac_start function
On Tue, Nov 26, 2024 at 05:28:08PM +0800, Frank Sae wrote:
>
>
> On 2024/11/26 11:15, Frank Sae wrote:
> > Hi Andrew,
> >
> > On 2024/11/25 22:18, Andrew Lunn wrote:
> >>>> RGMII is unusual, you normally want RGMII_ID. Where are the 2ns delays
> >>>> added?
> >>>>
> >>>
> >>> Yes, you are right. PHY_INTERFACE_MODE_RGMII should be PHY_INTERFACE_MODE_RGMII_ID.
> >>> YT6801 NIC integrated with YT8531S phy, and the 2ns delays added in the phy driver.
> >>> https://elixir.bootlin.com/linux/v6.12/source/drivers/net/phy/motorcomm.c#L895
> >>
> >> But if you pass PHY_INTERFACE_MODE_RGMII to the PHY it is not adding
> >> the 2ns delay. So how does this work now?
> >
> > I'm sorry. Maybe PHY_INTERFACE_MODE_RGMII is enough.
> > YT6801 is a pcie NIC chip that integrates one yt8531s phy.
> > Therefore, a delay of 2ns is unnecessary, as the hardware has
> > already ensured this.
>
> YT6801 looks like that:
>
> ||
> ********************++**********************
> * | PCIE Endpoint | *
> * +---------------+ *
> * | GMAC | *
> * +--++--+ YT6801 *
> * |**| *
> * GMII --> |**| <-- MDIO *
> * +-++--+ *
> * | PHY | *
> * +--++-+ *
> *********************||*********************
>
> yt8531s phy driver not support GMII.
Is it really GMII? If so, add GMII to the yt8531 driver.
Often this is described as PHY_INTERFACE_MODE_INTERNAL, meaning it
does not matter what is being used between the MAC and the PHY, it is
internal to the SoC. You might want to add that to the PHY driver.
Andrew
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