linux-kernel - Re: [PATCH v2 1/3] dt-bindings: can: fsl,flexcan: add S32G2/S32G3 SoC support

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Message-ID: <20241126-aquatic-brawny-shrimp-b3cc0e-mkl@pengutronix.de>
Date: Tue, 26 Nov 2024 16:18:41 +0100
From: Marc Kleine-Budde <mkl@...gutronix.de>
To: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
Cc: Krzysztof Kozlowski <krzk@...nel.org>, 
	Vincent Mailhol <mailhol.vincent@...adoo.fr>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, linux-can@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, NXP S32 Linux <s32@....com>, 
	imx@...ts.linux.dev, Christophe Lizzi <clizzi@...hat.com>, 
	Alberto Ruiz <aruizrui@...hat.com>, Enric Balletbo <eballetb@...hat.com>, 
	Frank Li <Frank.Li@....com>
Subject: Re: [PATCH v2 1/3] dt-bindings: can: fsl,flexcan: add S32G2/S32G3
 SoC support

On 26.11.2024 17:15:10, Ciprian Marian Costea wrote:
> > > > > > +        interrupt-names:
> > > > > > +          items:
> > > > > > +            - const: mb_0-7
> > 
> > I was wondering if it makes sense to have an interrupt name not
> > mentioning the exact mailbox numbers, so that the same interrupt name
> > can be used for a different IP core, too. On the coldfire SoC the 1st
> > IRQ handles mailboxes 0...15.
> > 
> 
> I am ok with proposing a more generic name for mailboxes in order to
> increase reusability among FlexCAN enabled SoCs.
> Further specific mailbox numbers could be mentioned in the actual
> S32G2/S32G3 dtsi flexcan node.
> 
> One proposal could be:
> - mb-1: First Range of Mailboxes
> - mb-2: Second Range of Mailboxes
> 
> Let me know if you agree to update as proposed in V3.

Looks good to me!

regards,
Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
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