linux-kernel - Re: [PATCH 1/3] dt-bindings: display/msm: gpu: Document A612 GPU

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <56b6f58e-e100-4dfd-b764-a9c3f5aad887@quicinc.com>
Date: Tue, 26 Nov 2024 20:54:26 +0530
From: Akhil P Oommen <quic_akhilpo@...cinc.com>
To: Krzysztof Kozlowski <krzk@...nel.org>, Rob Clark <robdclark@...il.com>,
        Sean Paul <sean@...rly.run>, Konrad Dybcio <konradybcio@...nel.org>,
        "Abhinav
 Kumar" <quic_abhinavk@...cinc.com>,
        Dmitry Baryshkov
	<dmitry.baryshkov@...aro.org>,
        Marijn Suijten
	<marijn.suijten@...ainline.org>,
        Maarten Lankhorst
	<maarten.lankhorst@...ux.intel.com>,
        Maxime Ripard <mripard@...nel.org>,
        Thomas Zimmermann <tzimmermann@...e.de>,
        David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
        Rob Herring <robh@...nel.org>,
        "Krzysztof
 Kozlowski" <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        "Bjorn
 Andersson" <andersson@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
        <freedreno@...ts.freedesktop.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/3] dt-bindings: display/msm: gpu: Document A612 GPU

On 11/26/2024 7:42 PM, Krzysztof Kozlowski wrote:
> On 26/11/2024 15:06, Akhil P Oommen wrote:
>> A612 GPU requires an additional smmu_vote clock. Update the bindings to
>> reflect this.
>>
>> Signed-off-by: Akhil P Oommen <quic_akhilpo@...cinc.com>
>> ---
>>  .../devicetree/bindings/display/msm/gpu.yaml       | 28 ++++++++++++----------
>>  1 file changed, 16 insertions(+), 12 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> index 6ddc72fd85b04537ea270754a897b4e7eb269641..201150d3151b55c26c95832d36f4e02f66060a25 100644
>> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> @@ -187,6 +187,7 @@ allOf:
>>              enum:
>>                - qcom,adreno-610.0
>>                - qcom,adreno-619.1
>> +              - qcom,adreno-612.0
> 
> Keep things ordered.

Ack.

> 
>>      then:
>>        properties:
>>          clocks:
>> @@ -195,18 +196,21 @@ allOf:
>>  
>>          clock-names:
>>            items:
>> -            - const: core
>> -              description: GPU Core clock
>> -            - const: iface
>> -              description: GPU Interface clock
>> -            - const: mem_iface
>> -              description: GPU Memory Interface clock
>> -            - const: alt_mem_iface
>> -              description: GPU Alternative Memory Interface clock
>> -            - const: gmu
>> -              description: CX GMU clock
>> -            - const: xo
>> -              description: GPUCC clocksource clock
>> +            anyOf:
> 
> No, this makes everything total mess. Why xo now is allowed to be first
> clock?
> 
> Drop and explain in commit msg why other devices now get smmu clock.

I thought it was okay to make this list a bit flexible. Btw, the other
existing clock-names list for a5x and older gpus uses "anyOf".

I suppose the suggestion is to add a separate clock-names list for A612
with strict ordering. Is that correct?

-Akhil

> 
> BTW, I am pretty sure this breaks existing platforms.
> 
> Best regards,
> Krzysztof