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Message-Id: <20241127103031.1007893-4-andrej.picej@norik.com>
Date: Wed, 27 Nov 2024 11:30:31 +0100
From: Andrej Picej <andrej.picej@...ik.com>
To: andrzej.hajda@...el.com,
neil.armstrong@...aro.org,
rfoss@...nel.org,
Laurent.pinchart@...asonboard.com,
jonas@...boo.se,
jernej.skrabec@...il.com,
airlied@...il.com,
simona@...ll.ch,
maarten.lankhorst@...ux.intel.com,
mripard@...nel.org,
tzimmermann@...e.de,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
shawnguo@...nel.org,
s.hauer@...gutronix.de,
kernel@...gutronix.de,
festevam@...il.com,
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Cc: dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org
Subject: [PATCH 3/3] arm64: dts: imx8mm-phyboard-polis-peb-av-10: Set custom lvds_vcom
Set custom differential output voltage for LVDS, to fulfill requirements
of the connected display. LVDS diferential voltage for data-lanes and
clock output has to be between 200 mV and 600 mV.
Driver sets 200 Ohm near-end termination by default and since
LVDS_VCOM_CHA_LVDS_VOD_SWING (0x19) [3:2] sets both data-lane and clock
output voltage we have to set the register to the value of 0x0C (0b11 <<
2):
- Steady-state differential output voltage for LVDS data-lanes:
min: 300 mV, typ: 402 mV, max: 511 mV
- Steady-state differential output voltage for LVDS clock lane:
min: 234 mV, typ: 314 mV, max: 399 mV
Signed-off-by: Andrej Picej <andrej.picej@...ik.com>
---
.../boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso
index a9de42cf14be..709b555ca753 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso
@@ -179,6 +179,7 @@ port@0 {
bridge_in: endpoint {
remote-endpoint = <&dsi_out>;
data-lanes = <1 2 3 4>;
+ ti,lvds-vcom = <0x0C>;
};
};
--
2.34.1
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