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Message-Id: <20241127-gs101-phy-lanes-orientation-dts-v1-3-5222d8508b71@linaro.org>
Date: Wed, 27 Nov 2024 11:01:41 +0000
From: André Draszik <andre.draszik@...aro.org>
To: Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Jagan Sridharan <badhri@...gle.com>,
Alim Akhtar <alim.akhtar@...sung.com>
Cc: Peter Griffin <peter.griffin@...aro.org>,
Tudor Ambarus <tudor.ambarus@...aro.org>,
Sam Protsenko <semen.protsenko@...aro.org>,
Will McVicker <willmcvicker@...gle.com>, Roy Luo <royluo@...gle.com>,
kernel-team@...roid.com, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-usb@...r.kernel.org,
devicetree@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
André Draszik <andre.draszik@...aro.org>
Subject: [PATCH 3/6] arm64: dts: exynos: gs101: phy region for
exynos5-usbdrd is larger
Turns out there are some additional registers in the phy region, update
the DT accordingly.
Signed-off-by: André Draszik <andre.draszik@...aro.org>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 302c5beb224a..18d4e7852a1a 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1267,7 +1267,7 @@ cmu_hsi0: clock-controller@...00000 {
usbdrd31_phy: phy@...00000 {
compatible = "google,gs101-usb31drd-phy";
- reg = <0x11100000 0x0100>,
+ reg = <0x11100000 0x0200>,
<0x110f0000 0x0800>,
<0x110e0000 0x2800>;
reg-names = "phy", "pcs", "pma";
--
2.47.0.338.g60cca15819-goog
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